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    Contacts for Nanowire Field Effect Transistors
    92.
    发明申请
    Contacts for Nanowire Field Effect Transistors 有权
    纳米线场效应晶体管的接触

    公开(公告)号：US20120037880A1

    公开(公告)日：2012-02-16

    申请号：US12856718

    申请日：2010-08-16

    申请人： Sarunya Bangsaruntip ,  Guy M. Cohen ,  Shreesh Narasimha ,  Jeffrey W. Sleight

    发明人： Sarunya Bangsaruntip ,  Guy M. Cohen ,  Shreesh Narasimha ,  Jeffrey W. Sleight

    IPC分类号： H01L29/775 ,  H01L21/336

    CPC分类号： H01L29/0673 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823412 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696 ,  Y10S977/938

    摘要： A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a semiconductor substrate, forming a gate stack around a portion of the nanowire, forming a capping layer on the gate stack, forming a spacer adjacent to sidewalls of the gate stack and around portions of nanowire extending from the gate stack, forming a hardmask layer on the capping layer and the first spacer, forming a metallic layer over the exposed portions of the device, depositing a conductive material over the metallic layer, removing the hardmask layer from the gate stack, and removing portions of the conductive material to define a source region contact and a drain region contact.

    摘要翻译： 一种形成纳米线场效应晶体管（FET）器件的方法包括在半导体衬底上形成纳米线，在纳米线的一部分周围形成栅叠层，在栅叠层上形成覆盖层，形成邻近于 栅极堆叠和从栅极堆叠延伸的纳米线的周围部分，在覆盖层和第一间隔物上形成硬掩模层，在器件的暴露部分上形成金属层，在金属层上沉积导电材料，去除硬掩模 层，并且去除导电材料的部分以限定源极区接触和漏极区接触。

    Self-aligned contacts for nanowire field effect transistors
    93.
    发明授权
    Self-aligned contacts for nanowire field effect transistors 有权
    纳米线场效应晶体管的自对准触点

    公开(公告)号：US08097515B2

    公开(公告)日：2012-01-17

    申请号：US12631213

    申请日：2009-12-04

    申请人： Sarunya Bangsaruntip ,  Guy M. Cohen ,  Shreesh Narasimha ,  Jeffrey W. Sleight

    发明人： Sarunya Bangsaruntip ,  Guy M. Cohen ,  Shreesh Narasimha ,  Jeffrey W. Sleight

    IPC分类号： H01L21/336 ,  H01L29/76

    CPC分类号： H01L29/775 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823418 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/458 ,  H01L29/66439 ,  H01L29/66772 ,  H01L29/78696

    摘要： A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a semiconductor substrate, forming a gate structure around a portion of the nanowire, forming a capping layer on the gate structure; forming a first spacer adjacent to sidewalls of the gate and around portions of nanowire extending from the gate, forming a hardmask layer on the capping layer and the first spacer, removing exposed portions of the nanowire, epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a source region and a drain region, forming a silicide material in the epitaxially grown doped semiconductor material, and forming a conductive material on the source and drain regions.

    摘要翻译： 形成纳米线场效应晶体管（FET）器件的方法包括在半导体衬底上形成纳米线，在纳米线的一部分周围形成栅极结构，在栅极结构上形成覆盖层; 形成邻近所述栅极的侧壁和从所述栅极延伸的纳米线的周围的第一间隔物，在所述覆盖层和所述第一间隔物上形成硬掩模层，去除所述纳米线的暴露部分，在暴露的横截面上外延生长掺杂半导体材料 以形成源极区和漏极区，在外延生长的掺杂半导体材料中形成硅化物材料，并在源极和漏极区上形成导电材料。

    Gate-All-Around Nanowire Tunnel Field Effect Transistors
    94.
    发明申请
    Gate-All-Around Nanowire Tunnel Field Effect Transistors 有权
    门 - 全能纳米线隧道场效应晶体管

    公开(公告)号：US20110133169A1

    公开(公告)日：2011-06-09

    申请号：US12630942

    申请日：2009-12-04

    申请人： Sarunya Bangsaruntip ,  Josephine B. Chang ,  Isaac Lauer ,  Jeffrey W. Sleight

    发明人： Sarunya Bangsaruntip ,  Josephine B. Chang ,  Isaac Lauer ,  Jeffrey W. Sleight

    IPC分类号： H01L29/12 ,  H01L21/336 ,  H01L29/78 ,  H01L29/08

    CPC分类号： H01L29/42392 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/78696

    摘要： A method for forming a nanowire tunnel field effect transistor (FET) device includes forming a nanowire suspended by first and second pad regions over a semiconductor substrate, the nanowire including a core portion and a dielectric layer, forming a gate structure around a portion of the dielectric layer, forming a first spacer around portions of the nanowire extending from the gate structure, implanting ions in a first portion of the nanowire, implanting ions in the dielectric layer of a second portion of the nanowire, removing the dielectric layer from the second portion of the nanowire, removing the core portion of the second portion of the exposed nanowire to form a cavity, and epitaxially growing a doped semiconductor material in the cavity from exposed cross sections of the nanowire and the second pad region to connect the exposed cross sections of the nanowire to the second pad region.

    摘要翻译： 一种形成纳米线隧道场效应晶体管（FET）器件的方法包括：在半导体衬底上形成由第一和第二衬垫区域悬挂的纳米线，纳米线包括芯部分和电介质层，在该部分的一部分周围形成栅极结构 电介质层，在从所述栅极结构延伸的所述纳米线的一部分周围形成第一间隔物，在所述纳米线的第一部分中注入离子，将所述离子注入到所述纳米线的第二部分的介电层中，从所述第二部分去除所述电介质层 去除所述暴露的纳米线的第二部分的核心部分以形成空腔，并且从所述纳米线和所述第二焊盘区域的暴露的横截面外延生长所述空腔中的掺杂半导体材料，以将所述暴露的横截面 纳米线到第二垫区域。

    Maskless Process for Suspending and Thinning Nanowires
    98.
    发明申请
    Maskless Process for Suspending and Thinning Nanowires 失效
    用于悬浮和稀释纳米线的无掩模工艺

    公开(公告)号：US20110108804A1

    公开(公告)日：2011-05-12

    申请号：US13006833

    申请日：2011-01-14

    申请人： Sarunya Bangsaruntip ,  Guy Cohen ,  Jeffrey W. Sleight

    发明人： Sarunya Bangsaruntip ,  Guy Cohen ,  Jeffrey W. Sleight

    IPC分类号： H01L29/775 ,  B82Y40/00

    CPC分类号： H01L29/775 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02667 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/78696 ,  Y10S977/762

    摘要： Semiconductor-based electronic devices and techniques for fabrication thereof are provided. In one aspect, a device is provided comprising a first pad; a second pad and a plurality of nanowires connecting the first pad and the second pad in a ladder-like configuration formed in a silicon-on-insulator (SOI) layer over a buried oxide (BOX) layer, the nanowires having one or more dimensions defined by a re-distribution of silicon from the nanowires to the pads. The device can comprise a field-effect transistor (FET) having a gate surrounding the nanowires wherein portions of the nanowires surrounded by the gate form channels of the FET, the first pad and portions of the nanowires extending out from the gate adjacent to the first pad form a source region of the FET and the second pad and portions of the nanowires extending out from the gate adjacent to the second pad form a drain region of the FET.

    摘要翻译： 提供了基于半导体的电子器件及其制造技术。 在一个方面，提供了一种包括第一垫的装置; 第二焊盘和多个纳米线，其以形成在掩埋氧化物（BOX）层上的绝缘体上硅（SOI）层中的梯形结构连接第一焊盘和第二焊盘，该纳米线具有一个或多个维度 由硅从纳米线重新分配到焊盘。 该器件可以包括具有围绕纳米线的栅极的场效应晶体管（FET），其中纳米线的部分由FET的栅极沟道围绕，第一焊盘和纳米线的部分从邻近第一 焊盘形成FET的源极区域，并且第二焊盘和从与第二焊盘相邻的栅极延伸出的纳米线的部分形成FET的漏极区域。

    Maskless Process for Suspending and Thinning Nanowires
    99.
    发明申请
    Maskless Process for Suspending and Thinning Nanowires 有权
    用于悬浮和稀释纳米线的无掩模工艺

    公开(公告)号：US20100193770A1

    公开(公告)日：2010-08-05

    申请号：US12365623

    申请日：2009-02-04

    申请人： Sarunya Bangsaruntip ,  Guy Cohen ,  Jeffrey W. Sleight

    发明人： Sarunya Bangsaruntip ,  Guy Cohen ,  Jeffrey W. Sleight

    IPC分类号： H01L29/78 ,  H01L21/4763 ,  H01L21/84

    CPC分类号： H01L29/775 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02667 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/78696 ,  Y10S977/762

    摘要： Semiconductor-based electronic devices and techniques for fabrication thereof are provided. In one aspect, a device is provided comprising a first pad; a second pad and a plurality of nanowires connecting the first pad and the second pad in a ladder-like configuration formed in a silicon-on-insulator (SOI) layer over a buried oxide (BOX) layer, the nanowires having one or more dimensions defined by a re-distribution of silicon from the nanowires to the pads. The device can comprise a field-effect transistor (FET) having a gate surrounding the nanowires wherein portions of the nanowires surrounded by the gate form channels of the FET, the first pad and portions of the nanowires extending out from the gate adjacent to the first pad form a source region of the FET and the second pad and portions of the nanowires extending out from the gate adjacent to the second pad form a drain region of the FET.

    摘要翻译： 提供了基于半导体的电子器件及其制造技术。 在一个方面，提供了一种包括第一垫的装置; 第二焊盘和多个纳米线，其以形成在掩埋氧化物（BOX）层上的绝缘体上硅（SOI）层中的梯形结构连接第一焊盘和第二焊盘，该纳米线具有一个或多个维度 由硅从纳米线重新分配到焊盘。 该器件可以包括具有围绕纳米线的栅极的场效应晶体管（FET），其中纳米线的部分由FET的栅极沟道围绕，第一焊盘和纳米线的部分从邻近第一 焊盘形成FET的源极区域，并且第二焊盘和从与第二焊盘相邻的栅极延伸出的纳米线的部分形成FET的漏极区域。