公开(公告)号：US06764941B2

公开(公告)日：2004-07-20

申请号：US10316709

申请日：2002-12-11

申请人： Won-Suk Yang ,  Yoo-Sang Hwang ,  Hong-Sik Jeong ,  Ki-Nam Kim

发明人： Won-Suk Yang ,  Yoo-Sang Hwang ,  Hong-Sik Jeong ,  Ki-Nam Kim

IPC分类号： H01L214763

CPC分类号： H01L21/76897 ,  H01L21/76829 ,  H01L21/76834 ,  H01L27/10882 ,  H01L27/10894

摘要： An etch-stop layer is selectively provided between layers of a multiple-layered circuit in a selective manner so as to allow for outgassing of impurities during subsequent fabrication processes. The etch-stop layer is formed over an underlying stud so as to serve as an alignment target during formation of an overlying stud formed in an upper layer. In this manner multiple-layered circuits, for example memory devices, can be fabricated in relatively dense configurations.

摘要翻译： 选择性地在多层电路的层之间选择性地提供蚀刻停止层，以便允许随后的制造过程中的杂质脱气。 蚀刻停止层形成在下面的螺柱上，以便在形成在上层中的上覆螺柱的形成期间用作对准目标。 以这种方式，可以以相对致密的配置制造多层电路，例如存储器件。

公开(公告)号：US06713310B2

公开(公告)日：2004-03-30

申请号：US10354651

申请日：2003-01-29

申请人： Yoon-Jong Song ,  Ki-Nam Kim ,  Sang-Woo Lee

发明人： Yoon-Jong Song ,  Ki-Nam Kim ,  Sang-Woo Lee

IPC分类号： H01G706

CPC分类号： H01L27/11502 ,  H01L27/11507

摘要： A ferroelectric memory device and a method for manufacturing the same. The ferroelectric memory device comprises a lower interlayer insulating layer formed on a semiconductor substrate. The ferroelectric memory device further comprises at least two adjacent ferroelectric capacitors disposed on the lower interlayer insulating layer, an interlayer insulation layer formed over the ferroelectric capacitors, leaving a top surface of the ferroelectric capacitors exposed, a patterned via etch-stop layer formed on the interlayer insulation layer, leaving the top surface of the capacitors exposed, an upper interlayer insulating layer formed on the patterned via etch-stop layer, and a plate line commonly connected to the at least two adjacent ferroelectric capacitors. Thus, integration of the ferroelectric memory device can be substantially increased.

公开(公告)号：US06594174B2

公开(公告)日：2003-07-15

申请号：US10003528

申请日：2001-10-30

申请人： Mun-Kyu Choi ,  Byung-Gil Jeon ,  Ki-Nam Kim

发明人： Mun-Kyu Choi ,  Byung-Gil Jeon ,  Ki-Nam Kim

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： A ferroelectric random access memory device of the present invention includes an access transistor having a gate connected to a word line and a current path connected between a bit line and an internal cell node. A ferroelectric capacitor is connected between the internal cell node and a plate line. A reference voltage generator for generating a reference voltage includes a linear paraelectric capacitor. Data stored in the ferroelectric capacitor is sensed by activating the word line so as to connect the ferroelectric capacitor to the bit line. The plate line is then activated and simultaneously the reference capacitor is connected to a complementary bit line. After a voltage difference between the bit line and the complementary bit line is detected, the reference capacitor is insulated from the complementary bit line.

公开(公告)号：US06391736B1

公开(公告)日：2002-05-21

申请号：US09704763

申请日：2000-11-03

申请人： Hyung-Soo Uh ,  Sang-Ho Song ,  Ki-Nam Kim

发明人： Hyung-Soo Uh ,  Sang-Ho Song ,  Ki-Nam Kim

IPC分类号： H01L2120

CPC分类号： H01L27/10855 ,  H01L27/10894 ,  H01L28/60 ,  H01L28/90

摘要： A method for fabricating a capacitor of a semiconductor device, and a capacitor made in accordance with the method are disclosed. The method includes forming a plate electrode polysilicon layer on a semiconductor substrate having a cell array region and a core/peripheral circuit region. The plate electrode polysilicon layer in the cell array region is patterned to form an opening, wherein the inner wall of the opening is used as a plate electrode. After forming a dielectric layer in the opening, a storage node is formed as a spacer on the dielectric layer on the inner wall of the opening. The plate electrode polysilicon layer in the core/peripheral circuit region remains to provide the same height between the cell array region where the cell capacitor is formed and the core/peripheral circuit region.

摘要翻译： 公开了一种制造半导体器件的电容器的方法和根据该方法制成的电容器。 该方法包括在具有单元阵列区域和核心/外围电路区域的半导体衬底上形成平板电极多晶硅层。 将单元阵列区域中的平板电极多晶硅层图案化以形成开口，其中开口的内壁用作平板电极。 在开口中形成电介质层之后，在开口的内壁上的电介质层上形成作为间隔物的存储节点。 芯/外围电路区域中的平板电极多晶硅层保持为在形成单元电容器的单元阵列区域和核心/外围电路区域之间提供相同的高度。

公开(公告)号：US06297090B1

公开(公告)日：2001-10-02

申请号：US09255293

申请日：1999-02-22

申请人： Ki-Nam Kim

发明人： Ki-Nam Kim

IPC分类号： H01L218242

CPC分类号： H01L27/10858 ,  H01L27/1082 ,  H01L27/10873 ,  H01L27/1203 ,  Y10S438/977

摘要： A method for fabricating a high-density semiconductor memory device which can reduce chip size and increase memory device characteristics. The present invention provides SOI type memory device. The capacitor is embedded in the insulator below the semiconductor wafer and the transistor is formed after the formation of the capacitor. As a result, the degradation of the transistor can be prevented, sufficiently increase the capacitor surface area, and provide fully planarized surface during the processing steps.

摘要翻译： 一种制造高密度半导体存储器件的方法，其可以减小芯片尺寸并增加存储器件特性。 本发明提供SOI型存储器件。 电容器嵌入在半导体晶片下面的绝缘体中，并且在形成电容器之后形成晶体管。 结果，可以防止晶体管的劣化，充分增加电容器表面积，并且在处理步骤期间提供完全平坦化的表面。

公开(公告)号：US08693245B2

公开(公告)日：2014-04-08

申请号：US13279451

申请日：2011-10-24

申请人： Ki-Tae Park ,  Ki-Nam Kim ,  Yeong-Taek Lee

发明人： Ki-Tae Park ,  Ki-Nam Kim ,  Yeong-Taek Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/0408 ,  G11C11/5621 ,  G11C16/0483 ,  G11C16/10 ,  G11C2211/5641 ,  G11C2211/5642

摘要： A flash memory device includes a plurality of memory blocks. A selected memory block among the plurality of memory blocks includes 2n pages of data. The selected memory block includes different types of memory cells capable of storing different numbers of bits.

摘要翻译： 闪存器件包括多个存储器块。 多个存储块中选择的存储块包括2n页的数据。 所选存储块包括能够存储不同位数的不同类型的存储单元。

公开(公告)号：US08258563B2

公开(公告)日：2012-09-04

申请号：US13049495

申请日：2011-03-16

申请人： Young-Chul Jang ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

发明人： Young-Chul Jang ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

IPC分类号： H01L29/76

CPC分类号： H01L27/105 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551

摘要： A nonvolatile memory device includes a semiconductor substrate having a first well region of a first conductivity type, and at least one semiconductor layer formed on the semiconductor substrate. A first cell array is formed on the semiconductor substrate, and a second cell array formed on the semiconductor layer. The semiconductor layer includes a second well region of the first conductivity type having a doping concentration greater than a doping concentration of the first well region of the first conductivity type. As the doping concentration of the second well region is increased, a resistance difference may be reduced between the first and second well regions.

摘要翻译： 非易失性存储器件包括具有第一导电类型的第一阱区和形成在半导体衬底上的至少一个半导体层的半导体衬底。 第一单元阵列形成在半导体衬底上，第二单元阵列形成在半导体层上。 半导体层包括第一导电类型的第二阱区，其具有大于第一导电类型的第一阱区的掺杂浓度的掺杂浓度。 随着第二阱区域的掺杂浓度增加，可以在第一和第二阱区域之间减小电阻差。

公开(公告)号：US07888198B1

公开(公告)日：2011-02-15

申请号：US09313659

申请日：1999-05-18

申请人： Won-Suk Yang ,  Ki-Nam Kim ,  Chang-Hyun Cho

发明人： Won-Suk Yang ,  Ki-Nam Kim ,  Chang-Hyun Cho

IPC分类号： H01L21/00

CPC分类号： H01L29/6659 ,  H01L21/823425 ,  H01L21/823864 ,  H01L27/092 ,  H01L27/10873 ,  H01L27/10894 ,  H01L29/6656

摘要： An improved source/drain junction configuration in a metal-oxide semiconductor transistor is provided, as well as a novel method for fabricating this junction. This configuration employs gate double sidewall spacers in the peripheral region and gate single sidewall spacers in the cell array region. The double sidewall spacers are advantageously formed to suppress the short channel effect, to prevent current leakage, and to reduce sheet resistance. The insulating layer used to form the second spacers in the peripheral region remains in the cell array region and serves as an etching stopper during the etching step of interlayer insulating layer for contact opening formation and also serves as a barrier layer during the step of silicidation formation. As a result the fabrication process of the resulting device is simplified.

摘要翻译： 提供了金属氧化物半导体晶体管中的改善的源极/漏极结结构以及用于制造该结的新颖方法。 该配置在外围区域中使用门双侧壁间隔物，并且在单元阵列区域中采用栅极单侧壁间隔物。 有利地形成双侧壁间隔物以抑制短沟道效应，防止电流泄漏，并降低薄层电阻。 用于在周边区域中形成第二间隔物的绝缘层保留在电池阵列区域中，并且在用于接触开口形成的层间绝缘层的蚀刻步骤期间用作蚀刻停止层，并且还用作硅化物形成步骤期间的阻挡层 。 结果，简化了所得装置的制造过程。

公开(公告)号：US07842571B2

公开(公告)日：2010-11-30

申请号：US11623269

申请日：2007-01-15

申请人： Dong-Hwa Kwak ,  Jae-Kwan Park ,  Jae-Hwang Sim ,  Jin-Ho Kim ,  Ki-Nam Kim

发明人： Dong-Hwa Kwak ,  Jae-Kwan Park ,  Jae-Hwang Sim ,  Jin-Ho Kim ,  Ki-Nam Kim

IPC分类号： H01L21/336

CPC分类号： H01L21/76897 ,  H01L21/76816 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529

摘要： In one embodiment a semiconductor device includes odd contacts and respective odd lines. Spacers are formed on sidewalls of the odd lines and even openings for even lines are formed by performing an etching process. Even contacts are formed in the even openings and then even lines are formed.

摘要翻译： 在一个实施例中，半导体器件包括奇数触点和相应的奇数行。 间隔物形成在奇数行的侧壁上，并且通过执行蚀刻工艺形成均匀线的均匀开口。 偶数触点形成在均匀开口中，然后形成均匀的线。

公开(公告)号：US07626228B2

公开(公告)日：2009-12-01

申请号：US11637686

申请日：2006-12-12

申请人： Jae-Kwan Park ,  Ki-Nam Kim ,  Soon-Moon Jung

发明人： Jae-Kwan Park ,  Ki-Nam Kim ,  Soon-Moon Jung

IPC分类号： H01L29/792 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11568 ,  H01L27/11578

摘要： A NAND-type nonvolatile memory device includes a semiconductor substrate and a first ground selection line and a first string selection line disposed on the substrate in parallel to each other. A plurality of parallel first word lines are interposed on the substrate between the first ground selection line and the first string selection line. A first impurity-doped region is formed in the semiconductor substrate adjacent to the first word lines, the first ground selection line, and the first string selection line. A first interlayer dielectric layer is disposed on the first ground selection line, the first string selection line, the plurality of first word lines, and the semiconductor substrate. An epitaxial contact plug contacts the semiconductor substrate through the first interlayer dielectric layer. A single crystalline semiconductor layer is disposed on the first interlayer dielectric layer that contacts the epitaxial contact plug. A plurality of parallel second word lines is disposed on the single crystalline semiconductor layer. A second impurity-doped region formed in the single crystalline semiconductor layer adjacent to the second word lines. A second interlayer dielectric layer is disposed on the plurality of second word lines and the single crystalline semiconductor layer.

摘要翻译： NAND型非易失性存储器件包括半导体衬底和彼此平行地布置在衬底上的第一接地选择线和第一串选择线。 在第一接地选择线和第一串选择线之间的基板上插入多个平行的第一字线。 在与第一字线，第一地选择线和第一串选择线相邻的半导体衬底中形成第一杂质掺杂区。 第一层间介电层设置在第一接地选择线，第一串选择线，多个第一字线和半导体衬底上。 外延接触插塞通过第一层间介电层与半导体衬底接触。 单晶半导体层设置在与外延接触插塞接触的第一层间电介质层上。 多个平行的第二字线布置在单晶半导体层上。 形成在与第二字线相邻的单晶半导体层中的第二杂质掺杂区。 第二层间介电层设置在多个第二字线和单晶半导体层上。