公开(公告)号：US08917104B2

公开(公告)日：2014-12-23

申请号：US13222306

申请日：2011-08-31

Applicant: Fen Chen ,  Roger A. Dufresne ,  Kai D. Feng ,  Richard J. St-Pierre

Inventor： Fen Chen ,  Roger A. Dufresne ,  Kai D. Feng ,  Richard J. St-Pierre

IPC: G01R31/3187 ,  G01R31/28

CPC classification number: G01R31/2858

Abstract: A testing structure, system and method for monitoring electro-migration (EM) performance. A system is described that includes an array of testing structures, wherein each testing structure includes: an EM resistor having four point resistive measurement, wherein a first and second terminals provide current input and a third and fourth terminals provide a voltage measurement; a first transistor coupled to a first terminal of the EM resistor for supplying a test current; the voltage measurement obtained from a pair of switching transistors whose gates are controlled by a selection switch and whose drains are utilized to provide a voltage measurement across the third and fourth terminals. Also included is a decoder for selectively activating the selection switch for one of the array of testing structures; and a pair of outputs for outputting the voltage measurement of a selected testing structure.

Abstract translation: 用于监测电迁移（EM）性能的测试结构，系统和方法。 描述了包括测试结构阵列的系统，其中每个测试结构包括：具有四点电阻测量的EM电阻器，其中第一和第二端子提供电流输入，第三和第四端子提供电压测量; 耦合到所述EM电阻器的第一端子以提供测试电流的第一晶体管; 由一对开关晶体管获得的电压测量，其栅极由选择开关控制，并且其漏极用于在第三和第四端子处提供电压测量。 还包括用于选择性地激活测试结构阵列之一的选择开关的解码器; 以及用于输出所选择的测试结构的电压测量的一对输出。

公开(公告)号：US08791728B2

公开(公告)日：2014-07-29

申请号：US13275369

申请日：2011-10-18

Applicant: John S. Austin ,  Kai D. Feng ,  Shiu Chung Ho ,  Zhenrong Jin

Inventor： John S. Austin ,  Kai D. Feng ,  Shiu Chung Ho ,  Zhenrong Jin

IPC: H03K21/00

CPC classification number: H03K19/1737 ,  H03K19/17744

Abstract: A dynamic latch has a pair of parallel pass gates (a first parallel pass gate that receives a seed signal, and a second parallel pass gate that receives a data signal). A first latch logic circuit performs logic operations using signals output by the parallel pass gates to produce an updated data signal. An additional pass gate is operatively connected to the first latch logic circuit. An additional pass gate controls passage of the updated data signal. An inverter receives the updated data signal from the pass gate, and inverts and outputs the updated data signal as an output data signal. Thus, the dynamic latch comprises two inputs into the pair of parallel pass gates and performs only one of four logical operations on a received data signal. The four logical operations are performed using the signals applied to the two inputs.

Abstract translation: 动态锁存器具有一对并行通道门（接收种子信号的第一并行通道门和接收数据信号的第二并行通道门）。 第一锁存逻辑电路使用由并行通道门输出的信号来执行逻辑运算以产生更新的数据信号。 附加的通过门可操作地连接到第一锁存逻辑电路。 一个附加的传递门控制更新的数据信号的通过。 反相器从传递门接收更新的数据信号，并将更新的数据信号反相并输出为输出数据信号。 因此，动态锁存器包括两对输入到该对并行通道门中，并且对接收到的数据信号仅执行四个逻辑运算中的一个。 使用施加到两个输入的信号来执行四个逻辑运算。

公开(公告)号：US08779838B2

公开(公告)日：2014-07-15

申请号：US13280666

申请日：2011-10-25

Applicant: Zhijian Yang ,  Ping-Chuan Wang ,  Kai D. Feng ,  Edwin J. Hostetter, Jr.

Inventor： Zhijian Yang ,  Ping-Chuan Wang ,  Kai D. Feng ,  Edwin J. Hostetter, Jr.

IPC: H03K17/687

CPC classification number: H01L29/66477 ,  G01R31/275 ,  H01L21/326 ,  H01L29/7833

Abstract: A method and apparatus for repairing transistors comprises applying a first voltage to a source, a second voltage to the gate and a third voltage to the drain for a predetermined time In this manner the semiconductor structure may be repaired or returned to the at or near the original operating characteristics.

Abstract translation: 用于修复晶体管的方法和装置包括向源极施加第一电压，向栅极施加第二电压并将第三电压施加到漏极达预定时间。以这种方式，半导体结构可以被修复或返回到位于或靠近 原有经营特点。

公开(公告)号：US08674423B2

公开(公告)日：2014-03-18

申请号：US13302168

申请日：2011-11-22

Applicant: David S. Collins ,  Kai D. Feng ,  Zhong-Xiang He ,  Peter J. Lindgren ,  Robert M. Rassel

Inventor： David S. Collins ,  Kai D. Feng ,  Zhong-Xiang He ,  Peter J. Lindgren ,  Robert M. Rassel

IPC: H01L27/108

CPC classification number: H01L29/945 ,  H01L23/481 ,  H01L23/5223 ,  H01L23/642 ,  H01L29/66181 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of making a semiconductor structure includes forming at least a first trench and a second trench having different depths in a substrate, forming a capacitor in the first trench, and forming a via in the second trench. A semiconductor structure includes a capacitor arranged in a first trench formed in a substrate and a via arranged in a second trench formed in the substrate. The first and second trenches have different depths in the substrate.

Abstract translation: 制造半导体结构的方法包括在衬底中形成至少具有不同深度的第一沟槽和第二沟槽，在第一沟槽中形成电容器，并在第二沟槽中形成通孔。 半导体结构包括布置在形成在衬底中的第一沟槽中的电容器和布置在形成于衬底中的第二沟槽中的通孔。 第一和第二沟槽在衬底中具有不同的深度。

公开(公告)号：US08589832B2

公开(公告)日：2013-11-19

申请号：US11844397

申请日：2007-08-24

Applicant: Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu

Inventor： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu

IPC: G06F17/50

CPC classification number: H05K9/0022

Abstract: An electromagnetic shielding structure that includes a conductive structure surrounding and accommodating a circuit or a circuit device arranged on a substrate. At least one feed through device is associated with the conductive structure and provides signals to the circuit or circuit device. The method includes forming a shielding structure so that the shielding structure at least one of is at least partially arranged within the substrate and surrounds the circuit or circuit device and associating at least one feed through device with the shielding structure.

Abstract translation: 一种电磁屏蔽结构，其包括围绕并容纳布置在基板上的电路或电路装置的导电结构。 至少一个馈送装置与导电结构相关联，并向电路或电路装置提供信号。 所述方法包括形成屏蔽结构，使得所述屏蔽结构至少部分地至少部分地布置在所述基板内并且围绕所述电路或电路装置并且将至少一个馈送装置与所述屏蔽结构相关联。

公开(公告)号：US08525549B1

公开(公告)日：2013-09-03

申请号：US13403339

申请日：2012-02-23

Applicant: Kai D. Feng ,  Hailing Wang ,  Ping-Chuan Wang ,  Zhijian Yang

Inventor： Kai D. Feng ,  Hailing Wang ,  Ping-Chuan Wang ,  Zhijian Yang

IPC: H03K19/173

CPC classification number: H03K5/156 ,  H03K5/1534

Abstract: A function cell comprising a first field effect transistor (FET) device, a second FET device, a first node connected to a gate terminal of the first FET device and a gate terminal of the second FET device, wherein the first node is operative to receive a voltage signal from an alternating current (AC) voltage source, an amplifier portion connected to the first FET device and the second FET device, the amplifier portion operative to receive a signal from the first FET device and the second FET device, a phase comparator portion having a first input terminal connected to an output terminal of the amplifier and a second input terminal operative to receive the voltage signal from the AC voltage source, the phase comparator portion operative to output a voltage indicative of a bit of a binary value.

Abstract translation: 一种功能单元，包括第一场效应晶体管（FET）器件，第二FET器件，连接到第一FET器件的栅极端子的第一节点和第二FET器件的栅极端子，其中第一节点可操作以接收 来自交流（AC）电压源的电压信号，连接到第一FET器件和第二FET器件的放大器部分，用于接收来自第一FET器件和第二FET器件的信号的放大器部分，相位比较器 部分具有连接到放大器的输出端子的第一输入端子和用于从AC电压源接收电压信号的第二输入端子，该相位比较器部分用于输出指示二进制值的位的电压。

公开(公告)号：US08519892B2

公开(公告)日：2013-08-27

申请号：US13534350

申请日：2012-06-27

Applicant: Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Zhenrong Jin ,  Xuefeng Liu

Inventor： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Zhenrong Jin ,  Xuefeng Liu

IPC: H01Q1/38 ,  H01Q19/10

CPC classification number: H01Q1/2283 ,  H01Q1/40 ,  H01Q9/26 ,  H01Q9/285 ,  H01Q19/108 ,  H01Q19/30

Abstract: A semiconductor chip integrating a transceiver, an antenna, and a receiver is provided. The transceiver is located on a front side of a semiconductor substrate. A through substrate via provides electrical connection between the transceiver and the receiver located on a backside of the semiconductor substrate. The antenna connected to the transceiver is located in a dielectric layer located on the front side of the substrate. The separation between the reflector plate and the antenna is about the quarter wavelength of millimeter waves, which enhances radiation efficiency of the antenna. An array of through substrate dielectric vias may be employed to reduce the effective dielectric constant of the material between the antenna and the reflector plate, thereby reducing the wavelength of the millimeter wave and enhance the radiation efficiency. A design structure for designing, manufacturing, or testing a design for such a semiconductor chip is also provided.

Abstract translation: 提供集成收发器，天线和接收器的半导体芯片。 收发器位于半导体衬底的前侧。 通过基底通孔提供收发器和位于半导体衬底背面的接收器之间的电连接。 连接到收发器的天线位于位于基板正面的电介质层中。 反射板与天线之间的间隔大约是毫米波的四分之一波长，这提高了天线的辐射效率。 可以采用贯穿衬底电介质通孔的阵列来降低天线和反射板之间材料的有效介电常数，由此减小毫米波的波长并提高辐射效率。 还提供了用于设计，制造或测试这种半导体芯片的设计的设计结构。

公开(公告)号：US20130099853A1

公开(公告)日：2013-04-25

申请号：US13280666

申请日：2011-10-25

Applicant: Zhijian Yang ,  Ping-Chuan Wang ,  Kai D. Feng ,  Edwin J. Hostetter, JR.

Inventor： Zhijian Yang ,  Ping-Chuan Wang ,  Kai D. Feng ,  Edwin J. Hostetter, JR.

IPC: G05F3/02 ,  H01L21/02

CPC classification number: H01L29/66477 ,  G01R31/275 ,  H01L21/326 ,  H01L29/7833

Abstract: A method and apparatus for repairing transistors comprises applying a first voltage to a source, a second voltage to the gate and a third voltage to the drain for a predetermined time In this manner the semiconductor structure may be repaired or returned to the at or near the original operating characteristics.

Abstract translation: 用于修复晶体管的方法和装置包括向源极施加第一电压，向栅极施加第二电压并将第三电压施加到漏极达预定时间。以这种方式，半导体结构可以被修复或返回到位于或靠近 原有经营特点。

公开(公告)号：US08274301B2

公开(公告)日：2012-09-25

申请号：US12610683

申请日：2009-11-02

Applicant: Kai D. Feng ,  Thomas J. Fleischman ,  Ping-Chuan Wang ,  Xiaojin Wei ,  Zhijian Yang

Inventor： Kai D. Feng ,  Thomas J. Fleischman ,  Ping-Chuan Wang ,  Xiaojin Wei ,  Zhijian Yang

IPC: G01R31/00 ,  G01R31/10

CPC classification number: G01R31/2856 ,  G01R31/2875

Abstract: An accelerated failure indicator embedded on a semiconductor chip includes an insulating region; a circuit located inside the insulating region; a heating element located inside the insulating region, the heating element configured to heat the circuit to a temperature higher than an operating temperature of the semiconductor chip; and a reliability monitor configured to monitor the circuit for degradation, and further configured to trigger an alarm in the event that the degradation of the circuit exceeds a predetermined threshold. A method of operating an accelerated failure indicator embedded on a semiconductor chip includes determining an operating temperature of the semiconductor chip; heating a circuit located inside an insulating region of the accelerated failure indicator to a temperature higher than the determined operating temperature; monitoring the circuit for degradation; and triggering an alarm in the event that the degradation of the circuit exceeds a predetermined threshold.

Abstract translation: 嵌入在半导体芯片上的加速故障指示器包括绝缘区域; 位于绝缘区域内的电路; 位于所述绝缘区域内的加热元件，所述加热元件构造成将所述电路加热至高于所述半导体芯片的工作温度的温度; 以及可靠性监视器，其被配置为监视所述电路的劣化，并且还被配置为在所述电路的劣化超过预定阈值的情况下触发警报。 一种操作嵌入在半导体芯片上的加速故障指示器的方法包括确定半导体芯片的工作温度; 将位于加速故障指示器的绝缘区域内的电路加热到高于所确定的工作温度的温度; 监控电路退化; 并且在电路的劣化超过预定阈值的情况下触发报警。

公开(公告)号：US20120218030A1

公开(公告)日：2012-08-30

申请号：US13034758

申请日：2011-02-25

Applicant: Fen Chen ,  Kai D. Feng ,  Zhong-Xiang He

Inventor： Fen Chen ,  Kai D. Feng ,  Zhong-Xiang He

IPC: H03K19/003

CPC classification number: H03K19/00307

Abstract: Managing reliability of a circuit that includes a plurality of duplicate components, with less than all of the components being active at any time during circuit operation, where reliability is managed by operating, by the circuit, with a first set of components that includes a predefined number of components; selecting, without altering circuit performance and in accordance with a circuit reliability protocol, a second set of components with which to operate, including activating an inactive component and deactivating an active component of the first set of components; and operating, by the circuit, with the second set of components.

Abstract translation: 管理包括多个重复部件的电路的可靠性，其中小于所有组件在电路操作期间的任何时间处于活动状态，其中可靠性由电路通过第一组组件来管理，该组件包括预定义的 组件数量; 根据电路可靠性协议选择不改变电路性能的第二组组件，包括激活非活动组件和去激活第一组组件的活动组件; 并通过电路与第二组元件一起操作。