公开(公告)号：US06643768B2

公开(公告)日：2003-11-04

申请号：US10216044

申请日：2002-08-09

申请人： Kumar Ganapathy ,  Ruban Kanapathipillai

发明人： Kumar Ganapathy ,  Ruban Kanapathipillai

IPC分类号： G06F9302

CPC分类号： G06F9/3877 ,  G06F9/3001 ,  G06F9/30072 ,  G06F9/30149 ,  G06F9/30189 ,  G06F9/381 ,  G06F9/382 ,  G06F9/3853 ,  G06F9/3885 ,  G06F15/8015

摘要： A dyadic digital signal processing (DSP) instruction processor including a first DSP functional block to execute a main operation of a dyadic DSP instruction and a second DSP functional block to execute a sub operation of the dyadic DSP instruction with data paths of each selectively configured to execute the main operation and the sub operation of the dyadic DSP instruction. A voice and data communication system has a first gateway and a second gateway coupled to a packetized network, each gateway having a network interface including the dyadic DSP instruction processor. An application specific signal processor with a signal processor having a first DSP functional block to execute a main operation of a dyadic DSP instruction and a second DSP functional block to execute a sub operation with multiplexers coupled to the first DSP functional block and the second DSP functional block to selectively configure data paths thereto.

摘要翻译： 一种二进制数字信号处理（DSP）指令处理器，包括执行二进制DSP指令的主要操作的第一DSP功能块和第二DSP功能块，以执行二进制DSP指令的子操作，其中数据路径被选择性地配置为 执行二进制DSP指令的主要操作和子操作。 语音和数据通信系统具有耦合到分组化网络的第一网关和第二网关，每个网关具有包括二进制DSP指令处理器的网络接口。 一种具有信号处理器的应用专用信号处理器，具有第一DSP功能块，以执行二进制DSP指令的主操作和第二DSP功能块，以执行与第一DSP功能块和第二DSP功能的多路复用器的子操作 块以有选择地配置数据路径。

公开(公告)号：US06442672B1

公开(公告)日：2002-08-27

申请号：US09163741

申请日：1998-09-30

申请人： Kumar Ganapathy

发明人： Kumar Ganapathy

IPC分类号： G06F506

CPC分类号： G06F9/3822 ,  G06F9/30145 ,  G06F9/30181 ,  G06F9/30196 ,  G06F9/3885 ,  G06F9/3897

摘要： The invention is a processing method and a processor architecture which contains multiple processors on the same silicon but which does not make a fixed compromise by statically assigning processing units to the processors but rather dynamically assigns such processing units so that they may be efficiently shared. The invention may provide the same functionality as was obtained with static allocation, and may be implemented on a single chip with much lower area for the same level of performance. The preferred architecture uses a mode bit that may be programatically set for passing control from a general purpose instruction decoder to a finite state machine. The preferred architecture further includes a multiplexer that uses the mode bit as its selection input.

摘要翻译： 本发明是一种处理方法和处理器架构，其包含相同硅上的多个处理器，但是通过将处理单元静态地分配给处理器而不会产生固定的折中，而是动态地分配这样的处理单元，使得它们可以被有效地共享。 本发明可以提供与通过静态分配获得的功能相同的功能，并且可以在具有相同水平的性能的较低面积的单个芯片上实现。 优选架构使用可以被编程设置用于将通用控制从通用指令解码器传递到有限状态机的模式位。 优选架构还包括使用模式位作为其选择输入的多路复用器。

公开(公告)号：US07159169B2

公开(公告)日：2007-01-02

申请号：US10660361

申请日：2003-09-11

申请人： Hooman Honary ,  Kumar Ganapathy ,  Amit R. Gupta ,  Siva Simanapalli

发明人： Hooman Honary ,  Kumar Ganapathy ,  Amit R. Gupta ,  Siva Simanapalli

IPC分类号： H03M13/03

CPC分类号： H03M13/6502 ,  H03M13/2957 ,  H03M13/4107 ,  H03M13/6511

摘要： An apparatus includes an instruction decoder, at least one control register coupled to the instruction decoder, and an add-compare-select (ACS) engine coupled to the at least one control register. The instruction decoder is operative to control the ACS engine to perform Viterbi decoding in response to the instruction decoder receiving a first instruction, and is operative to control the ACS engine to perform turbo decoding in response to the instruction decoder receiving a second instruction.

摘要翻译： 一种装置包括指令解码器，耦合到指令解码器的至少一个控制寄存器以及耦合到至少一个控制寄存器的加法比较选择（ACS）引擎。 指令解码器可操作以响应于指令解码器接收第一指令来控制ACS引擎执行维特比解码，并且可操作以响应于指令解码器接收第二指令来控制ACS引擎执行turbo解码。

公开(公告)号：US06988184B2

公开(公告)日：2006-01-17

申请号：US10211387

申请日：2002-08-02

申请人： Kumar Ganapathy ,  Ruban Kanapathipillai

发明人： Kumar Ganapathy ,  Ruban Kanapathipillai

IPC分类号： G06F9/302

CPC分类号： G06F9/3877 ,  G06F9/3001 ,  G06F9/30072 ,  G06F9/30149 ,  G06F9/30189 ,  G06F9/381 ,  G06F9/382 ,  G06F9/3853 ,  G06F9/3885 ,  G06F15/8015

摘要： Methods of performing dyadic digital signal processing (DSP) instructions. In one embodiment of the invention, the method includes fetching a dyadic DSP instruction having a main operation and a sub operation; predecoding the dyadic DSP instruction to generate predecoded instruction signals; and decoding the predecoded instruction signals to generate select signals to selectively couple data from a first plurality of buses coupled to inputs of multiplexers of a first plurality of DSP functional blocks to execute the main operation of the dyadic DSP instruction in one processor cycle and to selectively couple data from a second plurality of buses coupled to inputs of multiplexers of a second plurality of DSP functional blocks to execute the sub operation of the dyadic DSP instruction in the one processor cycle.

摘要翻译： 执行二进制数字信号处理（DSP）指令的方法。 在本发明的一个实施例中，该方法包括获取具有主操作和子操作的二进制DSP指令; 预编码二进制DSP指令以产生预解码指令信号; 以及解码所述预解码的指令信号以产生选择信号以选择性地耦合来自耦合到第一多个DSP功能块的多路复用器的输入的第一多个总线的数据，以在一个处理器周期中执行所述二进制DSP指令的主要操作，并且选择性地 耦合来自耦合到第二多个DSP功能块的多路复用器的输入的第二多个总线的数据，以在一个处理器周期中执行二进制DSP指令的子操作。

公开(公告)号：US06832306B1

公开(公告)日：2004-12-14

申请号：US09652593

申请日：2000-08-30

申请人： Kumar Ganapathy ,  Ruban Kanapathipillai

发明人： Kumar Ganapathy ,  Ruban Kanapathipillai

IPC分类号： G06F1516

CPC分类号： G06F17/10 ,  G06F7/49921 ,  G06F7/5318 ,  G06F7/5332 ,  G06F7/5443 ,  G06F9/3001 ,  G06F9/381 ,  G06F9/3877 ,  G06F9/3885

摘要： Disclosed is a method and apparatus for a unified RISC/DSP pipeline controller to control the execution of both reduced instruction set computer (RISC) control instructions and digital signal processing (DSP) instructions for a signal processor. The unified RISC/DSP pipeline controller is coupled to a program memory, a RISC control unit, and at least one signal processing unit. The program memory stores both DSP and RISC control instructions and the RISC control-unit controls the flow of operands and results between the signal processing unit and a data memory that stores data. The signal processing unit executes the DSP instruction. The unified RISC/DSP pipeline controller generates DSP control signals to control the execution of the DSP instruction by the signal processing unit and RISC control signals to control the execution of the RISC control instruction by the RISC control unit.

摘要翻译： 公开了一种统一的RISC / DSP流水线控制器来控制信号处理器的简化指令集计算机（RISC）控制指令和数字信号处理（DSP）指令的执行的方法和装置。 统一的RISC / DSP流水线控制器耦合到程序存储器，RISC控制单元和至少一个信号处理单元。 程序存储器存储DSP和RISC控制指令，并且RISC控制单元控制信号处理单元与存储数据的数据存储器之间的操作数和结果的流动。 信号处理单元执行DSP指令。 统一的RISC / DSP流水线控制器生成DSP控制信号，通过信号处理单元控制DSP指令的执行和RISC控制信号，以控制RISC控制单元执行RISC控制指令。

公开(公告)号：US06408376B1

公开(公告)日：2002-06-18

申请号：US09652100

申请日：2000-08-30

申请人： Kumar Ganapathy ,  Ruban Kanapathipillai

发明人： Kumar Ganapathy ,  Ruban Kanapathipillai

IPC分类号： G06F922

CPC分类号： G06F9/3877 ,  G06F7/49921 ,  G06F7/5318 ,  G06F7/5332 ,  G06F7/5443 ,  G06F9/3001 ,  G06F9/30025 ,  G06F9/30101 ,  G06F9/30138 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/30192 ,  G06F9/381 ,  G06F9/382 ,  G06F9/383 ,  G06F9/3842 ,  G06F9/3853 ,  G06F9/3885 ,  G06F17/10

摘要： Disclosed is a method, apparatus, and an instruction set architecture (ISA) for an application specific signal processor (ASSP) tailored to digital signal processing (DSP) applications. The instruction set architecture implemented with the ASSP, is adapted to DSP algorithmic structures. In one embodiment, a single DSP instruction includes a pair of sub-instructions: a primary DSP sub-instruction and a shadow DSP sub-instruction. Both the primary and the shadow DSP sub-instructions are dyadic DSP instructions performing two operations in one instruction cycle. The DSP operations, in one embodiment, include a multiply instruction (MULT), an addition instruction (ADD), a minimize/maximize instruction (MIN/MAX), and a no operation instruction (NOP). Each signal processing unit includes a primary stage to execute a primary DSP sub-instruction based upon current data and a shadow stage to simultaneously execute a shadow DSP sub-instruction based upon delayed data stored locally within registers of the signal processing units. Control logic is utilized to control shadow selectors of each signal processing unit to select delayed data (specified by the shadow DSP sub-instruction) for use by the shadows stages of the signal processing units. In this way, the present invention efficiently executes DSP instructions by simultaneously executing primary DSP sub-instructions (based upon current data) and shadow DSP sub-instructions (based upon delayed locally stored data) with a single DSP instruction thereby performing four operations per single instruction cycle.

摘要翻译： 公开了针对数字信号处理（DSP）应用定制的专用信号处理器（ASSP）的方法，装置和指令集架构（ISA）。 采用ASSP实现的指令集架构适用于DSP算法结构。 在一个实施例中，单个DSP指令包括一对子指令：主DSP子指令和阴影DSP子指令。 主要和阴影DSP子指令都是在一个指令周期内执行两个操作的二进制DSP指令。 在一个实施例中，DSP操作包括乘法指令（MULT），加法指令（ADD），最小化/最大化指令（MIN / MAX）和无操作指令（NOP）。 每个信号处理单元包括基于当前数据执行主DSP子指令的初级阶段和阴影阶段，以基于本地存储在信号处理单元的寄存器内的延迟数据来同时执行阴影DSP子指令。 控制逻辑用于控制每个信号处理单元的阴影选择器，以选择由信号处理单元的阴影级使用的延迟数据（由阴影DSP子指令指定）。 以这种方式，本发明通过使用单个DSP指令同时执行主DSP子指令（基于当前数据）和阴影DSP子指令（基于延迟本地存储的数据）来有效地执行DSP指令，从而每单个执行四个操作 指令周期。

公开(公告)号：US07318115B2

公开(公告)日：2008-01-08

申请号：US10649090

申请日：2003-08-27

申请人： Ruban Kanapathippillai ,  Kumar Ganapathy ,  Thu Nguyen ,  Siva Venkatraman ,  Earle F. Philhower, III ,  Manoj Mehta ,  Kenneth Malich

发明人： Ruban Kanapathippillai ,  Kumar Ganapathy ,  Thu Nguyen ,  Siva Venkatraman ,  Earle F. Philhower, III ,  Manoj Mehta ,  Kenneth Malich

IPC分类号： G06F12/00

CPC分类号： G06F1/3203 ,  G06F1/3237 ,  G06F1/3287 ,  G06F9/30072 ,  G06F9/30149 ,  G06F9/30181 ,  G06F9/381 ,  G06F9/382 ,  G06F9/3853 ,  G06F9/3877 ,  Y02D10/128 ,  Y02D10/171 ,  Y02D50/20

摘要： Method and apparatus for reducing power consumption in a digital specific signal processor integrated circuit. Data buses are routed through multiplexers to reduce the number of busses routed across an integrated circuit and maintain their prior state. Global memory is clustered into memory clusters. The memory cluster having a memory block to be accessed is activated without activating other memory clusters in the global memory. Inactive data buses retain their state by use of bus state keepers. A loop buffer stores instructions within program loops to avoid memory accesses. Functional blocks can have their clocks gated instruction by instruction to lower power consumption. RISC and DSP units swap circuit activity to reduce power consumption. Local data memory is includes self-timed memory access activation and provides for off boundary access to further lower power consumption.

摘要翻译： 用于降低数字特定信号处理器集成电路中的功耗的方法和装置。 数据总线通过多路复用器布线，以减少跨越集成电路布线的总线数量并保持其先前状态。 全局内存集群到内存集群中。 具有要访问的存储器块的存储器簇被激活而不激活全局存储器中的其他存储器簇。 非活动数据总线通过使用总线状态保持器保持其状态。 循环缓冲器在程序循环中存储指令以避免存储器访问。 功能块可以通过指令使其时钟门控指令降低功耗。 RISC和DSP单元交换电路活动以降低功耗。 本地数据存储器包括自定义存储器访问激活，并提供边界访问以进一步降低功耗。

公开(公告)号：US07062637B2

公开(公告)日：2006-06-13

申请号：US10382595

申请日：2003-03-06

申请人： Kumar Ganapathy ,  Ruban Kanapathipillai

发明人： Kumar Ganapathy ,  Ruban Kanapathipillai

IPC分类号： G00F9/302

CPC分类号： G06F9/383 ,  G06F5/00 ,  G06F7/4806 ,  G06F7/49921 ,  G06F7/5318 ,  G06F7/5332 ,  G06F7/5443 ,  G06F7/57 ,  G06F9/30014 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30072 ,  G06F9/30101 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30192 ,  G06F9/381 ,  G06F9/3816 ,  G06F9/382 ,  G06F9/3853 ,  G06F9/3877 ,  G06F9/3885 ,  G06F17/10

摘要： Executing digital signal processing (DSP) instructions in a digital signal processor integrated circuit comprising receiving a DSP instruction in digital signal processor integrated circuit to process one or more complex number operands; fetching a first operand with a first data type, the first operand having real and imaginary values with a complex data type; fetching a second operand with a second data type; prior to executing a DSP operation, determining a permutation of the first operand, the second operand, or both the first operand and the second operand, and permuting instances of the first operand, the second operand, or both the first operand and the second operand to execute the DSP operation; and executing the DSP operation in the digital signal processor integrated circuit using the first operand and the second operand to obtain a result, the result having real and imaginary values with a complex data type.

摘要翻译： 在数字信号处理器集成电路中执行数字信号处理（DSP）指令，包括在数字信号处理器集成电路中接收DSP指令以处理一个或多个复数操作数; 获取具有第一数据类型的第一操作数，所述第一操作数具有复数数据类型的实数值和虚数值; 获取具有第二数据类型的第二操作数; 在执行DSP操作之前，确定第一操作数，第二操作数或第一操作数和第二操作数的置换，以及置换第一操作数，第二操作数或第一操作数和第二操作数两者的实例 执行DSP操作; 并且使用第一操作数和第二操作数在数字信号处理器集成电路中执行DSP操作以获得结果，结果具有复数数据类型的实数和虚数值。

公开(公告)号：US20060112260A1

公开(公告)日：2006-05-25

申请号：US11323253

申请日：2005-12-30

申请人： Kumar Ganapathy ,  Ruban Kanapathipillai

发明人： Kumar Ganapathy ,  Ruban Kanapathipillai

IPC分类号： G06F9/30

CPC分类号： G06F9/3877 ,  G06F9/3001 ,  G06F9/30072 ,  G06F9/30149 ,  G06F9/30189 ,  G06F9/381 ,  G06F9/382 ,  G06F9/3853 ,  G06F9/3885 ,  G06F15/8015

摘要： An instruction set architecture (ISA) for application specific signal processor (ASSP) is tailored to digital signal processing applications. The instruction set architecture implemented with the ASSP, is adapted to DSP algorithmic structures. The instruction word of the ISA is typically 20 bits but can be expanded to 40-bits to control two instructions to be executed in series or parallel. All DSP instructions of the ISA are dyadic DSP instructions performing two operations with one instruction in one cycle. The DSP instructions or operations in the preferred embodiment include a multiply instruction (MULT), an addition instruction (ADD), a minimize/maximize instruction (MIN/MAX) also referred to as an extrema instruction, and a no operation instruction (NOP) each having an associated operation code (“opcode”). The present invention efficiently executes DSP instructions by means of the instruction set architecture and the hardware architecture of the application specific signal processor.

摘要翻译： 适用于特定于信号处理器（ASSP）的指令集体系结构（ISA）适用于数字信号处理应用。 采用ASSP实现的指令集架构适用于DSP算法结构。 ISA的指令字通常为20位，但可以扩展为40位，以控制串行或并行执行的两个指令。 ISA的所有DSP指令都是在一个周期内用一个指令执行两个操作的二进制DSP指令。 优选实施例中的DSP指令或操作包括乘法指令（MULT），加法指令（ADD），也称为极值指令的最小化/最大化指令（MIN / MAX）和无操作指令（NOP） 每个都具有相关联的操作代码（“操作码”）。 本发明通过指令集架构和应用专用信号处理器的硬件架构有效地执行DSP指令。

公开(公告)号：US20050060632A1

公开(公告)日：2005-03-17

申请号：US10660361

申请日：2003-09-11

申请人： Hooman Honary ,  Kumar Ganapathy ,  Amit Gupta ,  Siva Simanapalli

发明人： Hooman Honary ,  Kumar Ganapathy ,  Amit Gupta ,  Siva Simanapalli

IPC分类号： H03M13/03 ,  H03M13/41

CPC分类号： H03M13/6502 ,  H03M13/2957 ,  H03M13/4107 ,  H03M13/6511

摘要： An apparatus includes an instruction decoder, at least one control register coupled to the instruction decoder, and an add-compare-select (ACS) engine coupled to the at least one control register. The instruction decoder is operative to control the ACS engine to perform Viterbi decoding in response to the instruction decoder receiving a first instruction, and is operative to control the ACS engine to perform turbo decoding in response to the instruction decoder receiving a second instruction.

摘要翻译： 一种装置包括指令解码器，耦合到指令解码器的至少一个控制寄存器以及耦合到至少一个控制寄存器的加法比较选择（ACS）引擎。 指令解码器可操作以响应于指令解码器接收第一指令来控制ACS引擎执行维特比解码，并且可操作以响应于指令解码器接收第二指令来控制ACS引擎执行turbo解码。