公开(公告)号：US08476947B2

公开(公告)日：2013-07-02

申请号：US13295875

申请日：2011-11-14

申请人： John Henry Bui ,  Lay Hock Khoo ,  Khai Nguyen ,  Chiakang Sung ,  Ket Chiew Sia

发明人： John Henry Bui ,  Lay Hock Khoo ,  Khai Nguyen ,  Chiakang Sung ,  Ket Chiew Sia

IPC分类号： H03K3/017

CPC分类号： H03K5/1565 ,  H03K19/018592 ,  H03K19/09429

摘要： Integrated circuits with clock generation and distribution circuitry are provided. Integrated circuits may include phase-locked loops configured to generate multiple clock signals that are delayed versions of one another. The clocks signal may be distributed to various regions on an integrated circuit using serially connected clock buffer blocks. Each buffer block may include bidirectional pairs of buffer circuits coupled in parallel. Each buffer circuit may have a first input configured to receive an input clock signal, an output at which a corrected version of the input clock signal is provided (e.g., an output at which an output clock signal with desired duty cycle is provided), a second input that receives a first delayed clock signal for setting the desired duty cycle for the output clock signal, and a third input that receives a second delayed clock signal that is high at least when the first delayed clock signal rises high.

公开(公告)号：US20070165478A1

公开(公告)日：2007-07-19

申请号：US11558363

申请日：2006-11-09

申请人： Jeffrey Tyhach ,  Chiakang Sung ,  Khai Nguyen ,  Sanjay K. Charagulla ,  Ali Burney

发明人： Jeffrey Tyhach ,  Chiakang Sung ,  Khai Nguyen ,  Sanjay K. Charagulla ,  Ali Burney

IPC分类号： G11C8/00

CPC分类号： H03K19/17744

摘要： A programmable device I/O architecture allows for a variable number of I/O banks. Each I/O bank is of an I/O bank type. Each I/O bank type has a fixed number of I/O pins. I/O banks of the same I/O bank type are compatible within the same programmable device and between different types of programmable devices. The largest size I/O bank type and intermediate size I/O bank types are adapted to be a compatible supersets of every smaller I/O bank type. Support pins are regularly distributed between data pins in each I/O bank type. Multiple instances of the same or compatible I/O banks are arranged to be accessible from different sides of the programmable device. To facilitate circuit board layout, each I/O bank is arranged as a mirror and/or rotation of other I/O banks on the device.

摘要翻译： 可编程器件I / O架构允许可变数量的I / O bank。 每个I / O bank都是I / O bank类型。 每个I / O bank类型都有固定数量的I / O引脚。 相同I / O bank类型的I / O组在同一可编程器件内和不同类型的可编程器件之间兼容。 最大尺寸的I / O库类型和中等大小的I / O库类型适合于每个更小的I / O bank类型的兼容超集。 支持引脚定期分布在每个I / O bank类型的数据引脚之间。 相同或兼容的I / O组的多个实例被布置为可从可编程设备的不同侧面访问。 为了便于电路板布局，每个I / O组被布置为设备上的其他I / O组的镜像和/或旋转。

公开(公告)号：US09504156B1

公开(公告)日：2016-11-22

申请号：US11784540

申请日：2007-04-06

申请人： Gopinath Rangan ,  Khai Nguyen ,  Chiakang Sung

发明人： Gopinath Rangan ,  Khai Nguyen ,  Chiakang Sung

IPC分类号： H05K1/14 ,  H05K1/11 ,  H05K3/42

CPC分类号： H05K1/14 ,  H01L23/48 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/00 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/13101 ,  H05K1/0296 ,  H05K1/111 ,  H05K1/114 ,  H05K3/429 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/014 ,  H01L2924/00014

摘要： To achieve an even distribution of different types of connections, sets of connection cells have been devised having different ratios of signal, power and ground connections in which the signal connections are all within a maximum distance of a power and/or a ground connection. In addition, the shapes of the cells are such that the cells fit together in a repeatable array that fully covers the plane of the interface, i.e., an array that tiles the plane. Accordingly, to distribute the connections substantially uniformly across the interface, the ratio of the number of signal connections, power connections and ground connections is determined; a cell is selected from the set of cells that has approximately the same ratio of the number of signal connections, power connections and ground connections; and the selected cell is repeatedly used to allocate the signal, power and ground connections in accordance with the distribution of connections in the selected cell until all the connections are distributed.

摘要翻译： 为了实现不同类型的连接的均匀分配，已经设计了具有信号，功率和接地连接的不同比率的连接单元组，其中信号连接都在功率和/或接地连接的最大距离内。 此外，单元的形状使得这些单元以可完全覆盖界面的平面的可重复阵列（即平铺该平面的阵列）配合在一起。 因此，为了将连接基本均匀地分布在接口上，确定信号连接数量，电源连接和接地连接的数量比; 从具有大致相同的信号连接数，电源连接和接地连接的比例的单元组中选择一个单元; 并且所选择的小区被重复地用于根据所选小区中的连接的分布来分配信号，电源和接地连接，直到所有连接都分发为止。

公开(公告)号：US08630131B1

公开(公告)日：2014-01-14

申请号：US13562204

申请日：2012-07-30

申请人： Wilma Shiao ,  Warren Nordyke ,  Khai Nguyen ,  Chiakang Sung

发明人： Wilma Shiao ,  Warren Nordyke ,  Khai Nguyen ,  Chiakang Sung

IPC分类号： G11C5/14 ,  G11C7/06 ,  G11C7/00 ,  G11C8/16 ,  H03K17/16 ,  H03K19/003

CPC分类号： G11C7/1087 ,  G11C5/04 ,  G11C7/1051 ,  G11C7/1093 ,  H03K19/003 ,  H03K19/17724 ,  H03K23/40

摘要： An integrated circuit may include memory interface circuitry that is used to communicate with off-chip memory. The memory interface circuitry may include data strobe (DQS) enable circuitry that receives DQS signals from the off-chip memory and that outputs a gated version of the DQS signals. The DQS enable circuitry may include an input buffer, a comparator, a latch, a flip-flop, a counter, and a gating circuit. The input buffer may receive an incoming DQS signal. The comparator may be used to determine when the incoming DQS signal starts to toggle. The latch may be used to control when a gating signal is asserted. The flip-flop controls the counter, which limits the duration that the gating signal is asserted. The gating circuit receives the DQS signal from the buffer and the gating signal and passes the DQS signal through to its output only when the gating signal is asserted.

摘要翻译： 集成电路可以包括用于与片外存储器通信的存储器接口电路。 存储器接口电路可以包括从片外存储器接收DQS信号并输出​​DQS信号的选通版本的数据选通（DQS）使能电路。 DQS使能电路可以包括输入缓冲器，比较器，锁存器，触发器，计数器和门控电路。 输入缓冲器可以接收输入的DQS信号。 比较器可用于确定输入的DQS信号何时开始切换。 锁存器可用于控制门控信号何时被断言。 触发器控制计数器，这限制了门控信号被断言的持续时间。 门控电路从缓冲器和门控信号接收DQS信号，并且只有当门控信号被断言时才将DQS信号传递到其输出。

公开(公告)号：US07205788B1

公开(公告)日：2007-04-17

申请号：US11086979

申请日：2005-03-21

申请人： Bonnie I. Wang ,  Chiakang Sung ,  Khai Nguyen

发明人： Bonnie I. Wang ,  Chiakang Sung ,  Khai Nguyen

IPC分类号： H03K19/003

CPC分类号： H04L25/0278

摘要： The circuits and methods are provided for impedance termination on an integrated circuit. A network of resistors are formed on an integrated circuit (IC) to provide on-chip impedance termination to differential input/output (IO) pins. Transistors are coupled in the network of termination resistors. The transistors provide additional termination impedance to the differential IO pins. The transistors can be turned ON or OFF separately to change the impedance termination.

摘要翻译： 电路和方法用于集成电路上的阻抗终端。 在集成电路（IC）上形成电阻网络，为差分输入/输出（IO）引脚提供片内阻抗终端。 晶体管耦合在终端电阻网络中。 晶体管为差分IO引脚提供额外的终端阻抗。 晶体管可以单独打开或关闭，以改变阻抗终止。

公开(公告)号：US06888369B1

公开(公告)日：2005-05-03

申请号：US10622314

申请日：2003-07-17

申请人： Bonnie I. Wang ,  Chiakang Sung ,  Khai Nguyen

发明人： Bonnie I. Wang ,  Chiakang Sung ,  Khai Nguyen

IPC分类号： H03K19/003 ,  H04L25/02

CPC分类号： H04L25/0278

摘要： The circuits and methods are provided for impedance termination on an integrated circuit. A network of resistors are formed on an integrated circuit (IC) to provide on-chip impedance termination to differential input/output (IO) pins. Transistors are coupled in the network of termination resistors. The transistors provide additional termination impedance to the differential IO pins. The transistors can be turned ON or OFF separately to change the impedance termination.

摘要翻译： 电路和方法用于集成电路上的阻抗终端。 在集成电路（IC）上形成电阻网络，为差分输入/输出（IO）引脚提供片内阻抗终端。 晶体管耦合在终端电阻网络中。 晶体管为差分IO引脚提供额外的终端阻抗。 晶体管可以单独打开或关闭，以改变阻抗终止。

公开(公告)号：US07295040B1

公开(公告)日：2007-11-13

申请号：US11456569

申请日：2006-07-11

申请人： Khai Nguyen ,  Chiakang Sung ,  Gopi Rangan ,  Tzung-Chin Chang

发明人： Khai Nguyen ,  Chiakang Sung ,  Gopi Rangan ,  Tzung-Chin Chang

IPC分类号： H03K19/0175

CPC分类号： H03K19/17744 ,  H03K19/00315 ,  H03K19/1778 ,  H03K19/17784 ,  H03K19/17792

摘要： Circuits, methods, and apparatus that provide output drivers that consume relatively little integrated circuit area and provide fast output switching. An exemplary embodiment provides an output driver including pull-up and pull-down devices, each device driven by a pre-driver stage. The pre-driver for the pull-down device is supplied from an auxiliary power supply, which has a higher voltage than the supply seen by the pull-up device. The pre-driver for the pull-down is biased by a voltage that tracks the higher of the auxiliary and output supplies. In some embodiments, the output driver may be part of an input/output cell. In that case, the well for the pull-up device is biased by a voltage that tracks the highest of the output supply and input received voltage, while the pull-up predriver circuit bias is the higher between the auxiliary and output supplies and the input received voltage.

摘要翻译： 提供输出驱动器的电路，方法和装置，其消耗相对较小的集成电路面积并提供快速输出切换。 示例性实施例提供了包括上拉和下拉装置的输出驱动器，每个装置由预驱动器级驱动。 用于下拉装置的预驱动器由辅助电源供电，辅助电源的电压高于上拉装置所看到的电源电压。 用于下拉的预驱动器被跟踪较高的辅助和输出电源的电压偏置。 在一些实施例中，输出驱动器可以是输入/输出单元的一部分。 在这种情况下，上拉器件的阱被跟踪输出电源的最高电压和输入接收电压的电压偏置，而上拉预驱动电路偏置在辅助和输出电源和输入之间较高 接收电压。

公开(公告)号：US07088140B1

公开(公告)日：2006-08-08

申请号：US10794987

申请日：2004-03-04

申请人： Khai Nguyen ,  Chiakang Sung ,  Gopi Rangan ,  Tzung-Chin Chang

发明人： Khai Nguyen ,  Chiakang Sung ,  Gopi Rangan ,  Tzung-Chin Chang

IPC分类号： H03K19/0175

CPC分类号： H03K19/17744 ,  H03K19/00315 ,  H03K19/1778 ,  H03K19/17784 ,  H03K19/17792

摘要： Circuits, methods, and apparatus that provide output drivers that consume relatively little integrated circuit area and provide fast output switching. An exemplary embodiment provides an output driver including pull-up and pull-down devices, each device driven by a pre-driver stage. The pre-driver for the pull-down device is supplied from an auxiliary power supply, which has a higher voltage than the supply seen by the pull-up device. The pre-driver for the pull-down is biased by a voltage that tracks the higher of the auxiliary and output supplies. In some embodiments, the output driver may be part of an input/output cell. In that case, the well for the pull-up device is biased by a voltage that tracks the highest of the output supply and input received voltage, while the pull-up predriver circuit bias is the higher between the auxiliary and output supplies and the input received voltage.

摘要翻译： 提供输出驱动器的电路，方法和装置，其消耗相对较小的集成电路面积并提供快速输出切换。 示例性实施例提供了包括上拉和下拉装置的输出驱动器，每个装置由预驱动器级驱动。 用于下拉装置的预驱动器由辅助电源供电，辅助电源的电压高于上拉装置所看到的电源电压。 用于下拉的预驱动器被跟踪较高的辅助和输出电源的电压偏置。 在一些实施例中，输出驱动器可以是输入/输出单元的一部分。 在这种情况下，上拉器件的阱被跟踪输出电源的最高电压和输入接收电压的电压偏置，而上拉预驱动电路偏置在辅助和输出电源和输入之间较高 接收电压。

公开(公告)号：US08854078B1

公开(公告)日：2014-10-07

申请号：US13223989

申请日：2011-09-01

申请人： Xiaobao Wang ,  Bonnie I. Wang ,  Chiakang Sung ,  Khai Q. Nguyen

发明人： Xiaobao Wang ,  Bonnie I. Wang ,  Chiakang Sung ,  Khai Q. Nguyen

IPC分类号： H03K17/16

CPC分类号： H04L25/0298 ,  H04L25/0278

摘要： Circuits, methods, and apparatus for dynamic control of source and termination impedances. One output stage provides a series termination when transmitting and a parallel termination when receiving data. A pull-up device has a nominal impedance of 50 ohms when the output stage pulls a pin from a low voltage to a high voltage, while a pull-down device has a nominal impedance of 50 ohms when the pin is pulled from a high voltage to a low voltage. Both the pull-up and pull-down devices are turned on when receiving data. Due to their non-linear current-voltage characteristics, the pull-up device appears as 50 ohms when the pin voltage is higher than one half the supply voltage, while the pull-down device appears as 50 ohms when the pin voltage is lower than one half the supply voltage. The pull-up and pull-down devices can be calibrated to provide a nominal 50 ohm impedance.

摘要翻译： 用于动态控制源和端接阻抗的电路，方法和装置。 一个输出级在发送时提供串联终止，并在接收数据时提供并行终止。 当输出级将引脚从低电压拉到高电平时，上拉器件的标称阻抗为50欧姆，而当引脚从高电压拉出时，下拉器件的标称阻抗为50欧姆 到低电压。 上拉和下拉设备在接收数据时都打开。 由于其非线性电流 - 电压特性，当引脚电压高于电源电压的一半时，上拉器件显示为50欧姆，而当引脚电压低于50欧姆时，下拉器件显示为50欧姆 电源电压的一半。 可以校准上拉和下拉器件以提供标称的50欧姆阻抗。

公开(公告)号：US08022723B1

公开(公告)日：2011-09-20

申请号：US11458675

申请日：2006-07-19

申请人： Xiaobao Wang ,  Bonnie I. Wang ,  Chiakang Sung ,  Khai Q. Nguyen

发明人： Xiaobao Wang ,  Bonnie I. Wang ,  Chiakang Sung ,  Khai Q. Nguyen

IPC分类号： H03K17/16

CPC分类号： H04L25/0298 ,  H04L25/0278

摘要： Circuits, methods, and apparatus for dynamic control of source and termination impedances. One output stage provides a series termination when transmitting and a parallel termination when receiving data. A pull-up device has a nominal impedance of 50 ohms when the output stage pulls a pin from a low voltage to a high voltage, while a pull-down device has a nominal impedance of 50 ohms when the pin is pulled from a high voltage to a low voltage. Both the pull-up and pull-down devices are turned on when receiving data. Due to their non-linear current-voltage characteristics, the pull-up device appears as 50 ohms when the pin voltage is higher than one half the supply voltage, while the pull-down device appears as 50 ohms when the pin voltage is lower than one half the supply voltage. The pull-up and pull-down devices can be calibrated to provide a nominal 50 ohm impedance.

摘要翻译： 用于动态控制源和端接阻抗的电路，方法和装置。 一个输出级在发送时提供串联终止，并在接收数据时提供并行终止。 当输出级将引脚从低电压拉到高电平时，上拉器件的标称阻抗为50欧姆，而当引脚从高电压拉出时，下拉器件的标称阻抗为50欧姆 到低电压。 上拉和下拉设备在接收数据时都打开。 由于其非线性电流 - 电压特性，当引脚电压高于电源电压的一半时，上拉器件显示为50欧姆，而当引脚电压低于50欧姆时，下拉器件显示为50欧姆 电源电压的一半。 可以校准上拉和下拉器件以提供标称的50欧姆阻抗。