利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

128 条记录 (耗时 0.028 秒)

    Method for manufacturing semiconductor device having increased effective channel length
    91.
    发明授权
    Method for manufacturing semiconductor device having increased effective channel length 有权
    具有增加有效通道长度的半导体器件的制造方法

    公开(公告)号：US06815300B2

    公开(公告)日：2004-11-09

    申请号：US10427172

    申请日：2003-04-30

    申请人： Hong-Sik Jeong ,  Ki-Nam Kim ,  Yoo-Sang Hwang

    发明人： Hong-Sik Jeong ,  Ki-Nam Kim ,  Yoo-Sang Hwang

    IPC分类号： H01L21336

    CPC分类号： H01L27/10873 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10888 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

    摘要： In one embodiment, a plurality of gate structures including gate electrodes and insulating layers covering the gate electrodes are formed on a semiconductor substrate. Impurity ions at a low dose for forming a source/drain region are implanted into the semiconductor substrate, using the gate structures as a mask. First insulating spacers are formed on the sidewalls of the gate structures and second insulating spacers are formed on the first insulating spacers. Thereafter, impurity ions at a high dose are implanted into the semiconductor substrate, using the first and second insulating spacers as a mask. Then, the second insulating spacers are removed. Therefore, contact resistance and characteristics of the transistors can be improved by adjusting an effective channel length and contact areas.

    摘要翻译： 在一个实施例中，在半导体衬底上形成包括栅电极和覆盖栅电极的绝缘层的多个栅极结构。 使用栅极结构作为掩模，将用于形成源极/漏极区域的低剂量的杂质离子注入到半导体衬底中。 第一绝缘垫片形成在栅极结构的侧壁上，第二绝缘垫片形成在第一绝缘垫片上。 此后，使用第一和第二绝缘间隔物作为掩模，将高剂量的杂质离子注入到半导体衬底中。 然后，去除第二绝缘间隔物。 因此，可以通过调节有效沟道长度和接触面积来提高晶体管的接触电阻和特性。

    Ferroelectric memory device using via etch-stop layer and method for manufacturing the same
    93.
    发明授权
    Ferroelectric memory device using via etch-stop layer and method for manufacturing the same 失效

    公开(公告)号：US06713310B2

    公开(公告)日：2004-03-30

    申请号：US10354651

    申请日：2003-01-29

    申请人： Yoon-Jong Song ,  Ki-Nam Kim ,  Sang-Woo Lee

    发明人： Yoon-Jong Song ,  Ki-Nam Kim ,  Sang-Woo Lee

    IPC分类号： H01G706

    CPC分类号： H01L27/11502 ,  H01L27/11507

    摘要： A ferroelectric memory device and a method for manufacturing the same. The ferroelectric memory device comprises a lower interlayer insulating layer formed on a semiconductor substrate. The ferroelectric memory device further comprises at least two adjacent ferroelectric capacitors disposed on the lower interlayer insulating layer, an interlayer insulation layer formed over the ferroelectric capacitors, leaving a top surface of the ferroelectric capacitors exposed, a patterned via etch-stop layer formed on the interlayer insulation layer, leaving the top surface of the capacitors exposed, an upper interlayer insulating layer formed on the patterned via etch-stop layer, and a plate line commonly connected to the at least two adjacent ferroelectric capacitors. Thus, integration of the ferroelectric memory device can be substantially increased.

    Method for sensing data stored in a ferroelectric random access memory device
    94.
    发明授权
    Method for sensing data stored in a ferroelectric random access memory device 失效

    公开(公告)号：US06594174B2

    公开(公告)日：2003-07-15

    申请号：US10003528

    申请日：2001-10-30

    申请人： Mun-Kyu Choi ,  Byung-Gil Jeon ,  Ki-Nam Kim

    发明人： Mun-Kyu Choi ,  Byung-Gil Jeon ,  Ki-Nam Kim

    IPC分类号： G11C1122

    CPC分类号： G11C11/22

    摘要： A ferroelectric random access memory device of the present invention includes an access transistor having a gate connected to a word line and a current path connected between a bit line and an internal cell node. A ferroelectric capacitor is connected between the internal cell node and a plate line. A reference voltage generator for generating a reference voltage includes a linear paraelectric capacitor. Data stored in the ferroelectric capacitor is sensed by activating the word line so as to connect the ferroelectric capacitor to the bit line. The plate line is then activated and simultaneously the reference capacitor is connected to a complementary bit line. After a voltage difference between the bit line and the complementary bit line is detected, the reference capacitor is insulated from the complementary bit line.

    Method for fabricating a capacitor of a semiconductor device and a capacitor made thereby
    95.
    发明授权
    Method for fabricating a capacitor of a semiconductor device and a capacitor made thereby 有权
    制造半导体器件的电容器和由此制成的电容器的方法

    公开(公告)号：US06391736B1

    公开(公告)日：2002-05-21

    申请号：US09704763

    申请日：2000-11-03

    申请人： Hyung-Soo Uh ,  Sang-Ho Song ,  Ki-Nam Kim

    发明人： Hyung-Soo Uh ,  Sang-Ho Song ,  Ki-Nam Kim

    IPC分类号： H01L2120

    CPC分类号： H01L27/10855 ,  H01L27/10894 ,  H01L28/60 ,  H01L28/90

    摘要： A method for fabricating a capacitor of a semiconductor device, and a capacitor made in accordance with the method are disclosed. The method includes forming a plate electrode polysilicon layer on a semiconductor substrate having a cell array region and a core/peripheral circuit region. The plate electrode polysilicon layer in the cell array region is patterned to form an opening, wherein the inner wall of the opening is used as a plate electrode. After forming a dielectric layer in the opening, a storage node is formed as a spacer on the dielectric layer on the inner wall of the opening. The plate electrode polysilicon layer in the core/peripheral circuit region remains to provide the same height between the cell array region where the cell capacitor is formed and the core/peripheral circuit region.

    摘要翻译： 公开了一种制造半导体器件的电容器的方法和根据该方法制成的电容器。 该方法包括在具有单元阵列区域和核心/外围电路区域的半导体衬底上形成平板电极多晶硅层。 将单元阵列区域中的平板电极多晶硅层图案化以形成开口，其中开口的内壁用作平板电极。 在开口中形成电介质层之后，在开口的内壁上的电介质层上形成作为间隔物的存储节点。 芯/外围电路区域中的平板电极多晶硅层保持为在形成单元电容器的单元阵列区域和核心/外围电路区域之间提供相同的高度。

    Method for fabricating a high-density semiconductor memory device
    96.
    发明授权
    Method for fabricating a high-density semiconductor memory device 有权
    高密度半导体存储器件的制造方法

    公开(公告)号：US06297090B1

    公开(公告)日：2001-10-02

    申请号：US09255293

    申请日：1999-02-22

    申请人： Ki-Nam Kim

    发明人： Ki-Nam Kim

    IPC分类号： H01L218242

    CPC分类号： H01L27/10858 ,  H01L27/1082 ,  H01L27/10873 ,  H01L27/1203 ,  Y10S438/977

    摘要： A method for fabricating a high-density semiconductor memory device which can reduce chip size and increase memory device characteristics. The present invention provides SOI type memory device. The capacitor is embedded in the insulator below the semiconductor wafer and the transistor is formed after the formation of the capacitor. As a result, the degradation of the transistor can be prevented, sufficiently increase the capacitor surface area, and provide fully planarized surface during the processing steps.

    摘要翻译： 一种制造高密度半导体存储器件的方法，其可以减小芯片尺寸并增加存储器件特性。 本发明提供SOI型存储器件。 电容器嵌入在半导体晶片下面的绝缘体中，并且在形成电容器之后形成晶体管。 结果，可以防止晶体管的劣化，充分增加电容器表面积，并且在处理步骤期间提供完全平坦化的表面。

    Multi-layer memory devices
    98.
    发明授权
    Multi-layer memory devices 有权
    多层存储设备

    公开(公告)号：US08258563B2

    公开(公告)日：2012-09-04

    申请号：US13049495

    申请日：2011-03-16

    申请人： Young-Chul Jang ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

    发明人： Young-Chul Jang ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

    IPC分类号： H01L29/76

    CPC分类号： H01L27/105 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551

    摘要： A nonvolatile memory device includes a semiconductor substrate having a first well region of a first conductivity type, and at least one semiconductor layer formed on the semiconductor substrate. A first cell array is formed on the semiconductor substrate, and a second cell array formed on the semiconductor layer. The semiconductor layer includes a second well region of the first conductivity type having a doping concentration greater than a doping concentration of the first well region of the first conductivity type. As the doping concentration of the second well region is increased, a resistance difference may be reduced between the first and second well regions.

    摘要翻译： 非易失性存储器件包括具有第一导电类型的第一阱区和形成在半导体衬底上的至少一个半导体层的半导体衬底。 第一单元阵列形成在半导体衬底上，第二单元阵列形成在半导体层上。 半导体层包括第一导电类型的第二阱区，其具有大于第一导电类型的第一阱区的掺杂浓度的掺杂浓度。 随着第二阱区域的掺杂浓度增加，可以在第一和第二阱区域之间减小电阻差。

    Method of fabricating a MOS transistor with double sidewall spacers in a peripheral region and single sidewall spacers in a cell region
    99.
    发明授权
    Method of fabricating a MOS transistor with double sidewall spacers in a peripheral region and single sidewall spacers in a cell region 有权
    在周边区域中制造具有双重侧壁间隔物的MOS晶体管的方法和在单元区域中的单个侧壁间隔物

    公开(公告)号：US07888198B1

    公开(公告)日：2011-02-15

    申请号：US09313659

    申请日：1999-05-18

    申请人： Won-Suk Yang ,  Ki-Nam Kim ,  Chang-Hyun Cho

    发明人： Won-Suk Yang ,  Ki-Nam Kim ,  Chang-Hyun Cho

    IPC分类号： H01L21/00

    CPC分类号： H01L29/6659 ,  H01L21/823425 ,  H01L21/823864 ,  H01L27/092 ,  H01L27/10873 ,  H01L27/10894 ,  H01L29/6656

    摘要： An improved source/drain junction configuration in a metal-oxide semiconductor transistor is provided, as well as a novel method for fabricating this junction. This configuration employs gate double sidewall spacers in the peripheral region and gate single sidewall spacers in the cell array region. The double sidewall spacers are advantageously formed to suppress the short channel effect, to prevent current leakage, and to reduce sheet resistance. The insulating layer used to form the second spacers in the peripheral region remains in the cell array region and serves as an etching stopper during the etching step of interlayer insulating layer for contact opening formation and also serves as a barrier layer during the step of silicidation formation. As a result the fabrication process of the resulting device is simplified.

    摘要翻译： 提供了金属氧化物半导体晶体管中的改善的源极/漏极结结构以及用于制造该结的新颖方法。 该配置在外围区域中使用门双侧壁间隔物，并且在单元阵列区域中采用栅极单侧壁间隔物。 有利地形成双侧壁间隔物以抑制短沟道效应，防止电流泄漏，并降低薄层电阻。 用于在周边区域中形成第二间隔物的绝缘层保留在电池阵列区域中，并且在用于接触开口形成的层间绝缘层的蚀刻步骤期间用作蚀刻停止层，并且还用作硅化物形成步骤期间的阻挡层 。 结果，简化了所得装置的制造过程。