公开(公告)号：US08716814B2

公开(公告)日：2014-05-06

申请号：US11571859

申请日：2005-07-07

申请人： Shunpei Yamazaki ,  Kiyoshi Kato ,  Jun Koyama ,  Yutaka Shionoiri

发明人： Shunpei Yamazaki ,  Kiyoshi Kato ,  Jun Koyama ,  Yutaka Shionoiri

IPC分类号： H01L27/14

CPC分类号： H01L27/1222 ,  G06K19/0723 ,  H01L23/5387 ,  H01L23/66 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/13 ,  H01L29/78621 ,  H01L29/78648 ,  H01L2223/6677 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention provides a processor obtained by forming a high functional integrated circuit using a polycrystalline semiconductor over a substrate which is sensitive to heat, such as a plastic substrate or a plastic film substrate. Moreover, the invention provides a wireless processor, a wireless memory, and an information processing system thereof which transmit and receive power or signals wirelessly. According to the invention, an information processing system includes an element forming region including a transistor which has at least a channel forming region formed of a semiconductor film separated into islands with a thickness of 10 to 200 nm, and an antenna. The transistor is fixed on a flexible substrate. The wireless processor in which a high functional integrated circuit including the element forming region is formed and the semiconductor device transmit and receive data through the antenna.

摘要翻译： 本发明提供一种处理器，其通过在对热敏感的基板（例如塑料基板或塑料膜基板）上形成使用多晶半导体的高功能集成电路。 此外，本发明提供一种无线发送和接收电力或信号的无线处理器，无线存储器及其信息处理系统。 根据本发明，一种信息处理系统包括一个元件形成区域，该元件形成区域包括晶体管，该晶体管至少具有由半导体膜形成的沟道形成区域，半导体膜分隔成10至200nm的厚度的岛状物以及天线。 晶体管固定在柔性基板上。 其中形成包括元件形成区域的高功能集成电路并且半导体器件通过天线发送和接收数据的无线处理器。

公开(公告)号：US08680520B2

公开(公告)日：2014-03-25

申请号：US12949631

申请日：2010-11-18

申请人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

发明人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC分类号： H01L29/12

CPC分类号： H01L27/1203 ,  G11C11/403 ,  G11C11/405 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1156 ,  H01L27/1225

摘要： It is an object to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring, a second wiring, a third wiring, a fourth wiring, a first transistor including a first gate electrode, a first source electrode, and a first drain electrode, and a second transistor including a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided over a substrate including a semiconductor material, and the second transistor includes an oxide semiconductor layer.

摘要翻译： 本发明的目的是提供一种具有新颖结构的半导体器件。 半导体器件包括第一布线，第二布线，第三布线，第四布线，包括第一栅电极，第一源电极和第一漏电极的第一晶体管，以及包括第二栅电极的第二晶体管， 第二源电极和第二漏电极。 第一晶体管设置在包括半导体材料的衬底上，并且第二晶体管包括氧化物半导体层。

公开(公告)号：US08619470B2

公开(公告)日：2013-12-31

申请号：US13161616

申请日：2011-06-16

申请人： Kiyoshi Kato

发明人： Kiyoshi Kato

IPC分类号： G11C16/04

CPC分类号： G11C11/403 ,  G11C16/0433

摘要： A semiconductor device includes a source line, a bit line, and first to m-th (m is a natural number) memory cells connected in series between the source line and the bit line. Each of the first to m-th memory cells includes a first transistor having a first gate terminal, a first source terminal, and a first drain terminal, a second transistor having a second gate terminal, a second source terminal, and a second drain terminal, and a capacitor. The node of the k-th memory cell is supplied with a potential higher than that of the second gate terminal of the k-th memory cell in a data holding period in which the second gate terminal is supplied with a potential at which the second transistor is turned off.

摘要翻译： 半导体器件包括源极线，位线以及串联连接在源极线和位线之间的第一至第m（m为自然数）的存储单元。 第一至第m存储单元中的每一个包括具有第一栅极端子，第一源极端子和第一漏极端子的第一晶体管，具有第二栅极端子的第二晶体管，第二源极端子和第二漏极端子 ，和电容器。 第k个存储单元的节点在其第二栅极端子被提供有电位的数据保持周期中被提供有高于第k个存储单元的第二栅极端子的电位，在该电位下第二晶体管 已关闭

公开(公告)号：US08610187B2

公开(公告)日：2013-12-17

申请号：US12966611

申请日：2010-12-13

申请人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

发明人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC分类号： H01L27/105 ,  H01L27/108

CPC分类号： H01L27/115 ,  G11C16/0416 ,  H01L21/28518 ,  H01L23/528 ,  H01L27/10805 ,  H01L27/10855 ,  H01L27/11517 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L28/40 ,  H01L29/24 ,  H01L29/6659 ,  H01L29/78 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

摘要： A first transistor including a channel formation region, a first gate insulating layer, a first gate electrode, and a first source electrode and a first drain electrode; a second transistor including an oxide semiconductor layer, a second source electrode and a second drain electrode, a second gate insulating layer, and a second gate electrode; and a capacitor including one of the second source electrode and the second drain electrode, the second gate insulating layer, and an electrode provided to overlap with one of the second source electrode and the second drain electrode over the second gate insulating layer are provided. The first gate electrode and one of the second source electrode and the second drain electrode are electrically connected to each other.

公开(公告)号：US08598648B2

公开(公告)日：2013-12-03

申请号：US13044674

申请日：2011-03-10

申请人： Kiyoshi Kato ,  Satohiro Okamoto ,  Shuhei Nagatsuka

发明人： Kiyoshi Kato ,  Satohiro Okamoto ,  Shuhei Nagatsuka

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  G11C16/0408 ,  H01L27/115 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/13 ,  H01L28/60

摘要： A semiconductor device is formed using a material which allows a sufficient reduction in off-state current of a transistor; for example, an oxide semiconductor material, which is a wide-gap semiconductor, is used. When a semiconductor material which allows a sufficient reduction in off-state current of a transistor is used, the semiconductor device can hold data for a long time. Transistors each including an oxide semiconductor in memory cells of the semiconductor device are connected in series; thus, a source electrode of the transistor including an oxide semiconductor in the memory cell and a drain electrode of the transistor including an oxide semiconductor in the adjacent memory cell can be connected to each other. Therefore, the area occupied by the memory cells can be reduced.

摘要翻译： 使用允许充分降低晶体管的截止电流的材料形成半导体器件; 例如，使用作为宽间隙半导体的氧化物半导体材料。 当使用允许充分降低晶体管的截止电流的半导体材料时，半导体器件可以长时间保存数据。 各半导体装置的存储单元中的包含氧化物半导体的晶体管串联连接， 因此，包括存储单元中的氧化物半导体的晶体管的源极和在相邻的存储单元中包括氧化物半导体的晶体管的漏电极可以彼此连接。 因此，可以减少存储单元占用的面积。

公开(公告)号：US08576636B2

公开(公告)日：2013-11-05

申请号：US13175090

申请日：2011-07-01

申请人： Kiyoshi Kato ,  Takanori Matsuzaki ,  Hiroki Inoue ,  Shuhei Nagatsuka

发明人： Kiyoshi Kato ,  Takanori Matsuzaki ,  Hiroki Inoue ,  Shuhei Nagatsuka

IPC分类号： G11C11/34

CPC分类号： H01L27/1156 ,  G11C11/404 ,  G11C16/0441 ,  H01L27/1207

摘要： A plurality of memory cells included in a memory cell array are divided into a plurality of blocks every plural rows. A common bit line is electrically connected to the divided bit lines through selection transistors in the blocks. One of the memory cells includes a first transistor, a second transistor, and a capacitor. The first transistor includes a first channel formation region. The second transistor includes a second channel formation region. The first channel formation region includes a semiconductor material different from the semiconductor material of the second channel formation region.

摘要翻译： 包括在存储单元阵列中的多个存储单元被分成多个块，每个多行。 公共位线通过块中的选择晶体管电连接到分割位线。 一个存储单元包括第一晶体管，第二晶体管和电容器。 第一晶体管包括第一沟道形成区。 第二晶体管包括第二沟道形成区域。 第一沟道形成区域包括与第二沟道形成区域的半导体材料不同的半导体材料。

公开(公告)号：US08569753B2

公开(公告)日：2013-10-29

申请号：US13117588

申请日：2011-05-27

申请人： Atsuo Isobe ,  Yoshinori Ieda ,  Keitaro Imai ,  Kiyoshi Kato ,  Yuto Yakubo ,  Yuki Hata

发明人： Atsuo Isobe ,  Yoshinori Ieda ,  Keitaro Imai ,  Kiyoshi Kato ,  Yuto Yakubo ,  Yuki Hata

IPC分类号： H01L21/02

CPC分类号： H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/1225 ,  H01L28/60

摘要： The semiconductor device is provided in which a plurality of memory cells each including a first transistor, a second transistor, and a capacitor is arranged in matrix and a wiring (also referred to as a bit line) for connecting one of the memory cells and another one of the memory cells and a source or drain region in the first transistor are electrically connected through a conductive layer and a source or drain electrode in the second transistor provided therebetween. With this structure, the number of wirings can be reduced in comparison with a structure in which the source or drain electrode in the first transistor and the source or drain electrode in the second transistor are connected to different wirings. Thus, the integration degree of a semiconductor device can be increased.

摘要翻译： 提供了一种半导体器件，其中包括第一晶体管，第二晶体管和电容器的多个存储单元被布置成矩阵，并且布线（也称为位线）用于连接其中一个存储单元和另一个 第一晶体管中的一个存储单元和源极或漏极区域通过导电层和设置在其间的第二晶体管中的源极或漏极电连接。 利用这种结构，与第一晶体管中的源极或漏极以及第二晶体管中的源极或漏极连接到不同布线的结构相比，可以减少布线的数量。 因此，可以提高半导体器件的集成度。

公开(公告)号：US08549137B2

公开(公告)日：2013-10-01

申请号：US12308063

申请日：2007-05-28

申请人： Mitsuhiro Oono ,  Kiyoshi Kato

发明人： Mitsuhiro Oono ,  Kiyoshi Kato

IPC分类号： G06F15/00 ,  G06F17/18 ,  G06F11/30 ,  G06F11/00 ,  G06F15/177 ,  G06F15/173 ,  G06F13/00 ,  G06F9/44 ,  G06F9/46 ,  G06F17/00 ,  G05B11/01

CPC分类号： G06F11/30

摘要： Diverting condition storage unit 15 stores diverting conditions describing conditions for hardware configurations and software configurations. Monitoring data storage unit 13 stores monitoring data on the hardware configurations and the software configurations on monitored devices. Monitoring setting information storage unit stores monitoring setting information on the monitored devices. By referencing monitoring data and diverting conditions, first setting-diverting unit judges if monitoring setting information set in a monitored device may be diverted as monitoring setting information on another monitored device and outputs the result to a management terminal. The system administrator diverts the monitoring setting information among multiple monitored devices based on judgment result.

公开(公告)号：US08461586B2

公开(公告)日：2013-06-11

申请号：US13175542

申请日：2011-07-01

申请人： Shunpei Yamazaki ,  Kiyoshi Kato ,  Shuhei Nagatsuka

发明人： Shunpei Yamazaki ,  Kiyoshi Kato ,  Shuhei Nagatsuka

IPC分类号： H01L27/088

CPC分类号： H01L27/088 ,  G11C16/0433 ,  G11C16/26 ,  H01L27/11517 ,  H01L27/1156 ,  H01L27/1211 ,  H01L27/1225

摘要： A semiconductor device with a novel structure in which stored data can be retained even when power is not supplied, and does not have a limitation on the number of write cycles. The semiconductor device includes a memory cell including a first transistor, a second transistor, and an insulating layer placed between a source region or a drain region of the first transistor and a channel formation region of the second transistor. The first transistor and the second transistor are provided to at least partly overlap with each other. The insulating layer and a gate insulating layer of the second transistor satisfy the following formula: (ta/tb)×(∈ra/∈rb)

摘要翻译： 具有新颖结构的半导体器件，其中即使在未提供电力的情况下也可以保留存储的数据，并且对写入周期的数量没有限制。 半导体器件包括存储单元，其包括第一晶体管，第二晶体管和放置在第一晶体管的源极区域或漏极区域与第二晶体管的沟道形成区域之间的绝缘层。 第一晶体管和第二晶体管被设置为至少部分地彼此重叠。 第二晶体管的绝缘层和栅极绝缘层满足下式：（ta / tb）×（Erb / Era）<0.1，其中，ta表示栅极绝缘层的厚度，tb表示绝缘层的厚度 时，代表栅极绝缘层的介电常数，Erb表示绝缘层的介电常数。

公开(公告)号：US08441841B2

公开(公告)日：2013-05-14

申请号：US13027546

申请日：2011-02-15

申请人： Shuhei Nagatsuka ,  Kiyoshi Kato ,  Takanori Matsuzaki ,  Hiroki Inoue

发明人： Shuhei Nagatsuka ,  Kiyoshi Kato ,  Takanori Matsuzaki ,  Hiroki Inoue

IPC分类号： G11C11/24

CPC分类号： G11C8/08 ,  G11C11/413

摘要： An object is to provide a semiconductor device with a novel structure, which can hold stored data even when not powered and which has an unlimited number of write cycles. A semiconductor device includes a memory cell including a widegap semiconductor, for example, an oxide semiconductor and the semiconductor device includes a potential conversion circuit which functions to output a potential lower than a reference potential for reading data from the memory cell. With the use of a widegap semiconductor, a semiconductor device capable of sufficiently reducing the off-state current of a transistor included in a memory cell and capable of holding data for a long time can be provided.

摘要翻译： 目的是提供一种具有新颖结构的半导体器件，其即使在未被供电且具有无限数量的写周期的情况下也可以保存存储的数据。 半导体器件包括具有宽栅半导体例如氧化物半导体的存储单元，并且该半导体器件包括用于输出低于用于从存储单元读取数据的参考电位的电位的电位转换电路。 通过使用宽栅半导体，可以提供能够充分降低包含在存储单元中并能够长时间保持数据的晶体管的截止电流的半导体器件。