公开(公告)号：US08476626B2

公开(公告)日：2013-07-02

申请号：US12949641

申请日：2010-11-18

申请人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

发明人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC分类号： H01L51/10

CPC分类号： H01L21/02554 ,  G11C11/403 ,  G11C11/405 ,  G11C16/0425 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/02664 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1225

摘要： It is an object to provide a semiconductor device with a novel structure. The semiconductor device includes memory cells connected to each other in series and a capacitor. One of the memory cells includes a first transistor connected to a bit line and a source line, a second transistor connected to a signal line and a word line, and a capacitor connected to the word line. The second transistor includes an oxide semiconductor layer. A gate electrode of the first transistor, one of a source electrode and a drain electrode of the second transistor, and one electrode of the capacitor are connected to one another.

摘要翻译： 本发明的目的是提供一种具有新颖结构的半导体器件。 半导体器件包括彼此串联连接的存储单元和电容器。 一个存储单元包括连接到位线和源极线的第一晶体管，连接到信号线和字线的第二晶体管，以及连接到字线的电容器。 第二晶体管包括氧化物半导体层。 第一晶体管的栅电极，第二晶体管的源电极和漏电极之一以及电容器的一个电极彼此连接。

公开(公告)号：US20120161127A1

公开(公告)日：2012-06-28

申请号：US13331645

申请日：2011-12-20

申请人： Kiyoshi Kato ,  Jun Koyama ,  Toshihiko Saito ,  Shunpei Yamazaki

发明人： Kiyoshi Kato ,  Jun Koyama ,  Toshihiko Saito ,  Shunpei Yamazaki

IPC分类号： H01L29/78

CPC分类号： H01L27/1156 ,  G11C11/404 ,  H01L27/1225

摘要： The first transistor includes first and second electrodes which are a source and a drain, and a first gate electrode overlapping with a first channel formation region with an insulating film provided therebetween. The second transistor includes third and fourth electrodes which are a source and a drain, and a second channel formation region which is provided between a second gate electrode and a third gate electrode with insulating films provided between the second channel formation region and the second gate electrode and between the second channel formation region and the third gate electrode. The first and second channel formation regions contain an oxide semiconductor, and the second electrode is connected to the second gate electrode.

摘要翻译： 第一晶体管包括作为源极和漏极的第一和第二电极，以及与第一沟道形成区域重叠的第一栅电极，其间设置有绝缘膜。 第二晶体管包括作为源极和漏极的第三和第四电极以及设置在第二栅电极和第三栅极之间的第二沟道形成区，其中设置在第二沟道形成区和第二栅电极之间的绝缘膜 并且在第二通道形成区域和第三栅电极之间。 第一和第二沟道形成区域包含氧化物半导体，并且第二电极连接到第二栅电极。

公开(公告)号：US20110147737A1

公开(公告)日：2011-06-23

申请号：US12966611

申请日：2010-12-13

申请人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

发明人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC分类号： H01L29/12

CPC分类号： H01L27/115 ,  G11C16/0416 ,  H01L21/28518 ,  H01L23/528 ,  H01L27/10805 ,  H01L27/10855 ,  H01L27/11517 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L28/40 ,  H01L29/24 ,  H01L29/6659 ,  H01L29/78 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

摘要： A first transistor including a channel formation region, a first gate insulating layer, a first gate electrode, and a first source electrode and a first drain electrode; a second transistor including an oxide semiconductor layer, a second source electrode and a second drain electrode, a second gate insulating layer, and a second gate electrode; and a capacitor including one of the second source electrode and the second drain electrode, the second gate insulating layer, and an electrode provided to overlap with one of the second source electrode and the second drain electrode over the second gate insulating layer are provided. The first gate electrode and one of the second source electrode and the second drain electrode are electrically connected to each other.

摘要翻译： 第一晶体管，包括沟道形成区域，第一栅极绝缘层，第一栅极电极和第一源极电极以及第一漏极电极; 第二晶体管，包括氧化物半导体层，第二源极和第二漏极，第二栅极绝缘层和第二栅电极; 并且设置包括第二源电极和第二漏电极之一的电容器，第二栅极绝缘层和设置成与第二栅极绝缘层上的第二源电极和第二漏极之一重叠的电极。 第一栅极电极和第二源极电极和第二漏极电极中的一个彼此电连接。

公开(公告)号：US20110128777A1

公开(公告)日：2011-06-02

申请号：US12952609

申请日：2010-11-23

申请人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

发明人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC分类号： G11C11/24 ,  H01L29/12 ,  G11C7/00

CPC分类号： G11C11/405 ,  G11C16/0425 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1225

摘要： The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is formed on or in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.

摘要翻译： 半导体器件包括第一布线; 第二布线 第三线; 第四布线 具有第一栅电极，第一源电极和第一漏电极的第一晶体管; 以及具有第二栅电极，第二源电极和第二漏电极的第二晶体管。 第一晶体管形成在包括半导体材料的衬底上或衬底中。 第二晶体管包括氧化物半导体层。

公开(公告)号：US20110121286A1

公开(公告)日：2011-05-26

申请号：US12949641

申请日：2010-11-18

申请人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

发明人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC分类号： H01L27/092

CPC分类号： H01L21/02554 ,  G11C11/403 ,  G11C11/405 ,  G11C16/0425 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/02664 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1225

摘要： It is an object to provide a semiconductor device with a novel structure. The semiconductor device includes memory cells connected to each other in series and a capacitor. One of the memory cells includes a first transistor connected to a bit line and a source line, a second transistor connected to a signal line and a word line, and a capacitor connected to the word line. The second transistor includes an oxide semiconductor layer. A gate electrode of the first transistor, one of a source electrode and a drain electrode of the second transistor, and one electrode of the capacitor are connected to one another.

摘要翻译： 本发明的目的是提供一种具有新颖结构的半导体器件。 半导体器件包括彼此串联连接的存储单元和电容器。 一个存储单元包括连接到位线和源极线的第一晶体管，连接到信号线和字线的第二晶体管，以及连接到字线的电容器。 第二晶体管包括氧化物半导体层。 第一晶体管的栅电极，第二晶体管的源电极和漏电极之一以及电容器的一个电极彼此连接。

公开(公告)号：US20110116310A1

公开(公告)日：2011-05-19

申请号：US12945476

申请日：2010-11-12

申请人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

发明人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC分类号： G11C11/4096

CPC分类号： G11C7/062 ,  G11C7/067 ,  G11C11/40 ,  G11C2207/005 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1225 ,  H01L29/155 ,  H01L29/205

摘要： A semiconductor device includes: a source line; a bit line; a word line; a memory cell connected to the bit line and the word line; a driver circuit which drives a plurality of second signal lines and a plurality of word lines so as to select the memory cell specified by an address signal; a potential generating circuit which generates a writing potential and a plurality of reading potentials to supply to a writing circuit and a reading circuit; and a control circuit which selects one of a plurality of voltages for correction on a basis of results of the reading circuit comparing a potential of the bit line with the plurality of reading potentials.

摘要翻译： 半导体器件包括：源极线; 有点线 字线 连接到位线和字线的存储单元; 驱动电路，其驱动多个第二信号线和多个字线，以选择由地址信号指定的存储单元; 产生写入电位和多个读取电位以供应到写入电路和读取电路的电位产生电路; 以及控制电路，其基于将所述位线的电位与所述多个读取电位进行比较的所述读取电路的结果来选择用于校正的多个电压中的一个。

公开(公告)号：US06914818B2

公开(公告)日：2005-07-05

申请号：US10383209

申请日：2003-03-06

申请人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

发明人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC分类号： G11C16/02 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/00

CPC分类号： G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32

摘要： There is provided a non-volatile memory which enables high accuracy threshold control in a writing operation. In the present invention, a drain voltage and a drain current of a memory transistor are controlled to carry out a writing operation of a hot electron injection system, which is wherein a charge injection speed does not depend on a threshold voltage. FIGS. 1A and 1B are views of a circuit structure for controlling the writing. In FIGS. 1A and 1B, an output of an operational amplifier 103 is connected to a control gate of a memory transistor 101, a constant current source 102 is connected to a drain electrode, and a source electrode is grounded. The constant current source 102 and a voltage Vpgm are respectively connected to two input terminals of the operational amplifier 103.

摘要翻译： 提供了一种在写入操作中实现高精度阈值控制的非易失性存储器。 在本发明中，控制存储晶体管的漏极电压和漏极电流，进行热电子注入系统的写入动作，其中电荷注入速度不依赖于阈值电压。 图 图1A和1B是用于控制写入的电路结构的视图。 在图 如图1A和1B所示，运算放大器103的输出端连接到存储晶体管101的控制栅极，恒流源102连接到漏电极，源电极接地。 恒流源102和电压Vpgm分别连接到运算放大器103的两个输入端。

公开(公告)号：US08896042B2

公开(公告)日：2014-11-25

申请号：US12914672

申请日：2010-10-28

申请人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

发明人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC分类号： H01L27/108 ,  H01L29/94 ,  G11C16/04 ,  H01L27/12 ,  H01L27/118 ,  H01L27/115 ,  H01L27/105 ,  G11C11/405 ,  H01L29/78 ,  H01L21/822 ,  H01L27/06

CPC分类号： H01L27/1052 ,  G11C11/405 ,  G11C16/0433 ,  G11C2211/4016 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/11803 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/16 ,  H01L29/24 ,  H01L29/247 ,  H01L29/7833 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696

摘要： An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.

摘要翻译： 目的是提供具有新颖结构的半导体器件。 半导体器件包括第一布线; 第二布线 第三线; 第四布线 具有第一栅电极，第一源电极和第一漏电极的第一晶体管; 以及具有第二栅电极，第二源电极和第二漏电极的第二晶体管。 第一晶体管设置在包括半导体材料的衬底中。 第二晶体管包括氧化物半导体层。

公开(公告)号：US08872331B2

公开(公告)日：2014-10-28

申请号：US13084996

申请日：2011-04-12

申请人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato ,  Takaaki Koen ,  Yuto Yakubo ,  Makoto Yanagisawa ,  Hisashi Ohtani ,  Eiji Sugiyama ,  Nozomi Horikoshi

发明人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato ,  Takaaki Koen ,  Yuto Yakubo ,  Makoto Yanagisawa ,  Hisashi Ohtani ,  Eiji Sugiyama ,  Nozomi Horikoshi

IPC分类号： H01L23/10 ,  H01L23/31 ,  H01L23/29

CPC分类号： G06K19/07735 ,  G06K19/07722 ,  G06K19/07794 ,  H01L23/295 ,  H01L23/3157 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00

摘要： A semiconductor device capable of wireless communication, which has high reliability in terms of resistance to external force, in particular, pressing force and can prevent electrostatic discharge in an integrated circuit without preventing reception of an electric wave. The semiconductor device includes an on-chip antenna connected to the integrated circuit and a booster antenna which transmits a signal or power included in a received electric wave to the on-chip antenna without contact. In the semiconductor device, the integrated circuit and the on-chip antenna are interposed between a pair of structure bodies formed by impregnating a fiber body with a resin. One of the structure bodies is provided between the on-chip antenna and the booster antenna. A conductive film having a surface resistance value of approximately 106 to 1014 Ω/cm2 is formed on at least one surface of each structure body.

摘要翻译： 一种能够进行无线通信的半导体装置，其在外力方面具有高的可靠性，特别是按压力，并且能够防止集成电路中的静电放电，而不会妨碍电波的接收。 半导体器件包括连接到集成电路的片上天线和将接收到的电波中包含的信号或功率发送到片上天线而不接触的增强天线。 在半导体器件中，集成电路和片上天线插入通过用树脂浸渍纤维体而形成的一对结构体之间。 其中一个结构体设置在片上天线和增强天线之间。 在每个结构体的至少一个表面上形成表面电阻值为大约106至1014Ω·cm 2 / cm 2的导电膜。

公开(公告)号：US08576620B2

公开(公告)日：2013-11-05

申请号：US12945476

申请日：2010-11-12

申请人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

发明人： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC分类号： G11C11/40 ,  G11C11/401

CPC分类号： G11C7/062 ,  G11C7/067 ,  G11C11/40 ,  G11C2207/005 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1225 ,  H01L29/155 ,  H01L29/205

摘要： A semiconductor device includes: a source line; a bit line; a word line; a memory cell connected to the bit line and the word line; a driver circuit which drives a plurality of second signal lines and a plurality of word lines so as to select the memory cell specified by an address signal; a potential generating circuit which generates a writing potential and a plurality of reading potentials to supply to a writing circuit and a reading circuit; and a control circuit which selects one of a plurality of voltages for correction on a basis of results of the reading circuit comparing a potential of the bit line with the plurality of reading potentials.

摘要翻译： 半导体器件包括：源极线; 有点线 字线 连接到位线和字线的存储单元; 驱动电路，其驱动多个第二信号线和多个字线，以选择由地址信号指定的存储单元; 产生写入电位和多个读取电位以供给写入电路和读取电路的电位产生电路; 以及控制电路，其基于将所述位线的电位与所述多个读取电位进行比较的所述读取电路的结果来选择用于校正的多个电压中的一个。