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公开(公告)号：US11205481B2
公开(公告)日：2021-12-21
申请号：US17218243
申请日：2021-03-31
摘要： Memory devices might include control circuitry that, when checking for a match of a stored digit of data and a received digit of data, might be configured to cause the memory device to apply a first voltage level to a control gate of a first memory cell of a memory cell pair, apply a second voltage level different than the first voltage level to a control gate of a second memory cell of that memory cell pair, determine whether that memory cell pair is deemed to be activated or deactivated in response to applying the first and second voltage levels, and deem a match between the stored digit of data and a received digit of data in response, in part, to whether that memory cell pair is deemed to be deactivated.
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公开(公告)号：US20210304829A1
公开(公告)日：2021-09-30
申请号：US17344141
申请日：2021-06-10
发明人： Tommaso Vali , Ramin Ghodsi
摘要： Memories might include a plurality of strings of memory cells, a plurality of access lines each connected to the strings of memory cells, and a controller configured to cause the memory to determine a particular voltage level applied to each of the access lines that is deemed to activate each memory cell of a first subset of the strings of series-connected memory cells programmed to store respective data states that are each lower than or equal to a first data state of a plurality of data states, apply the particular voltage level to a particular access line of the plurality of access lines, and for each memory cell connected to the particular access line that is contained in a second subset of the strings of series-connected memory cells, determine whether that memory cell is deemed to be activated while applying the particular voltage level to the particular access line.
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公开(公告)号：US11107536B2
公开(公告)日：2021-08-31
申请号：US16916216
申请日：2020-06-30
发明人： Tommaso Vali , Luca De Santis , Ramin Ghodsi
摘要： Memory having a controller configured to cause the memory to determine a plurality of activation voltage levels for the plurality of memory cells, determine a plurality of activation voltage level distributions based on a subset of the plurality of activation voltage levels with each of the activation voltage level distributions corresponding to a respective first subset of memory cells of a plurality of first subsets of memory cells of the plurality of memory cells, determine a plurality of transition voltage levels based on the plurality of activation voltage level distributions, and assign a respective data state of a plurality of data states to each memory cell of a second subset of memory cells of the plurality of memory cells based on the determined activation voltage of that memory cell and the determined plurality of transition voltage levels.
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公开(公告)号：US20210202020A1
公开(公告)日：2021-07-01
申请号：US17202398
申请日：2021-03-16
发明人： Violante Moschiano , Tecla Ghilardi , Tommaso Vali , Emilio Camerlenghi , William C. Filipiak , Andrea D'Alessandro
IPC分类号： G11C16/34 , G11C16/26 , G11C8/08 , G11C11/413 , G11C5/06
摘要： Memories having a controller configured, during a pre-charge portion of a read operation, to apply a sequence of increasing voltage levels concurrently to each access line of a plurality of access lines, wherein each voltage level of the sequence of increasing voltage levels is higher than any previous voltage level of the sequence of increasing voltage levels and lower than any subsequent voltage level of the sequence of increasing voltage levels, and determine a particular voltage level of the sequence of increasing voltage levels corresponding to a point at which all memory cells of the plurality of strings of series-connected memory cells are first deemed to be activated while applying the sequence of increasing voltage levels.
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公开(公告)号：US20210065825A1
公开(公告)日：2021-03-04
申请号：US17095291
申请日：2020-11-11
发明人： Tommaso Vali , Ramin Ghodsi
摘要： Memory might include a plurality of strings of memory cells, a plurality of access lines each connected to the strings of memory cells, and a controller configured to cause the memory to increase a voltage level applied to each of the access lines, determine a particular voltage level at which each memory cell of a first set of strings of memory cells is deemed to be activated while increasing the voltage level applied to the access lines, decrease the voltage level applied to a particular access line without decreasing the voltage level applied to each remaining access line, and, for each memory cell connected to the particular access line and contained in a second set of strings of memory cells, determine whether that memory cell is deemed to be activated while applying the particular voltage level to the particular access line.
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公开(公告)号：US10861551B2
公开(公告)日：2020-12-08
申请号：US16235066
申请日：2018-12-28
发明人： Umberto Minucci , Tommaso Vali , Fernanda Irrera , Luca De Santis
摘要： A method can include applying a first voltage to a first memory cell to activate the first memory cell, applying a second voltage to a second memory cell coupled in series with the first memory cell to activate the second memory cell so that current flows through the first and second memory cells, and generating an output responsive to the current. The first voltage and a threshold voltage of the second memory cell can be such that the current is proportional to a product of the first voltage and the threshold voltage of the second memory cell.
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公开(公告)号：US20200335171A1
公开(公告)日：2020-10-22
申请号：US16916216
申请日：2020-06-30
发明人： Tommaso Vali , Luca De Santis , Ramin Ghodsi
摘要： Memory having a controller configured to cause the memory to determine a plurality of activation voltage levels for the plurality of memory cells, determine a plurality of activation voltage level distributions based on a subset of the plurality of activation voltage levels with each of the activation voltage level distributions corresponding to a respective first subset of memory cells of a plurality of first subsets of memory cells of the plurality of memory cells, determine a plurality of transition voltage levels based on the plurality of activation voltage level distributions, and assign a respective data state of a plurality of data states to each memory cell of a second subset of memory cells of the plurality of memory cells based on the determined activation voltage of that memory cell and the determined plurality of transition voltage levels.
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公开(公告)号：US20190340066A1
公开(公告)日：2019-11-07
申请号：US16516611
申请日：2019-07-19
IPC分类号： G06F11/10 , G11C29/52 , G06F3/06 , G06F12/06 , G11C16/04 , G06F12/02 , G11C16/10 , G11C11/56
摘要： A memory device has a plurality of individually erasable blocks of memory cells and a controller configured to configure a first block of memory cells of the plurality of blocks of memory cells in a first configuration comprising one or more groups of overhead data memory cells, to configure a second block of memory cells of the plurality of blocks of memory cells in a second configuration comprising a group of user data memory cells and a group of overhead data memory cells, and to configure a third block of memory cells of the plurality of blocks of memory cells in a third configuration comprising only a group of user data memory cells. The group of overhead data memory cells of the second block of memory cells has a different storage capacity than at least one group of overhead data memory cells of the one or more groups of overhead data memory cells of the first block of memory cells.
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99.发明申请公开(公告)号：US20190325971A1
公开(公告)日：2019-10-24
申请号：US16458384
申请日：2019-07-01
摘要： Methods of operating a memory device include comparing input data to data stored in memory cells coupled to a data line, comparing a representation of a level of current in the data line to a reference, and determining that the input data potentially matches the data stored in the memory cells when the representation of the level of current in the data line is less than the reference. Methods of operating a memory device further include comparing input data to first data and to second data stored in memory cells coupled to a first data line or to a second data line, respectively, comparing representations of the levels of current in the first data line and in the second data line to a first reference and to a different second reference, and deeming one to be a closer match to the input data in response to results of the comparisons.
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公开(公告)号：US10141055B2
公开(公告)日：2018-11-27
申请号：US15841490
申请日：2017-12-14
摘要： Methods include receiving a pattern to be searched in a memory having a plurality of sets of memory elements with each set coupled to a separate data line and corresponding to a same set of bit positions of the pattern. Methods further include receiving a pattern of data to be programmed into a memory, programming a first data state into one memory cell of each cell pair of a plurality of cell pairs of a memory array, and programing a second data state into another memory cell of each cell pair of the plurality of cell pairs for each bit position of the pattern. Memory configured to facilitate such methods include a plurality of cell pairs, each cell pair of the plurality of cell pairs programmed to store a same bit of data corresponding to a particular bit position of a pattern to be searched in the memory.
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