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公开(公告)号：US07470577B2
公开(公告)日：2008-12-30
申请号：US11204235
申请日：2005-08-15
IPC分类号： H01L21/00
CPC分类号： H01L21/823842 , H01L21/28088 , H01L29/4966
摘要： Concurrently forming different metal gate transistors having respective work functions is disclosed. In one example, a metal carbide, which has a relatively low work function, is formed over a semiconductor substrate. Oxygen and/or nitrogen are then added to the metal carbide in a second region to establish a second work function in the second region, where the metal carbide itself establishes a first work function in a first region. One or more first metal gate transistor types are then formed in the first region and one or more second metal gate transistor types are formed in the second region.
摘要翻译： 同时形成具有各自功函数的不同金属栅极晶体管。 在一个实例中，在半导体衬底上形成具有较低功函数的金属碳化物。 然后在第二区域中将氧和/或氮添加到金属碳化物中以在第二区域中建立第二功函数，其中金属碳化物本身在第一区域中建立第一功函数。 然后在第一区域中形成一个或多个第一金属栅极晶体管类型，并且在第二区域中形成一个或多个第二金属栅极晶体管类型。
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公开(公告)号：US07423326B2
公开(公告)日：2008-09-09
申请号：US11118647
申请日：2005-04-28
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L29/792
CPC分类号： H01L21/823842 , H01L21/823857
摘要： CMOS gate dielectric made of high-k metal silicates by passivating a silicon surface with nitrogen compounds prior to high-k dielectric deposition. Optionally, a silicon dioxide monolayer may be preserved at the interface.
摘要翻译： 在高k电介质沉积之前，用氮化合物钝化硅表面，由高k金属硅酸盐制成的CMOS栅极电介质。 任选地，二氧化硅单层可以在界面处保留。
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93.发明申请公开(公告)号：US20080157228A1
公开(公告)日：2008-07-03
申请号：US11618650
申请日：2006-12-29
CPC分类号： H01L21/28079 , H01L21/823842 , H01L21/823857 , H01L29/495
摘要： Exemplary embodiments provide structures and fabrication methods for dual work function metal gate electrodes. The work function value of a metal gate electrode can be increased and/or decreased by disposing various electronegative species and/or electropositive species at the metal/dielectric interface to control interface dipoles. In an exemplary embodiment, various electronegative species can be disposed at the metal/dielectric interface to increase the work function value of the metal, which can be used for a PMOS metal gate electrode in a dual work function gated device. Various electropositive species can be disposed at the metal/dielectric interface to decrease the work function value of the metal, which can be used for an NMOS metal gate electrode in the dual work function gated device.
摘要翻译： 示例性实施例提供了用于双功能金属栅电极的结构和制造方法。 通过在金属/电介质界面处设置各种电负性物质和/或正电性物质来控制界面偶极子，可以增加和/或降低金属栅电极的功函数值。 在示例性实施例中，各种电负性物质可以设置在金属/电介质界面处以增加金属的功函数值，其可用于双功能门控器件中的PMOS金属栅电极。 可以在金属/电介质界面处设置各种正电性物质，以降低金属的功函数值，这可以用于双功能门控器件中的NMOS金属栅电极。
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94.发明授权Semiconductor CMOS devices and methods with NMOS high-k dielectric present in core region that mitigate damage to dielectric materials 有权具有NMOS高k电介质的半导体CMOS器件和方法存在于芯区中，可减轻介电材料的损坏公开(公告)号：US07176076B2
公开(公告)日：2007-02-13
申请号：US11118843
申请日：2005-04-29
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823842 , Y10S438/981
摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. An I/O dielectric layer is formed in core and I/O regions of a semiconductor device (506). The I/O dielectric layer is removed (508) from the core region of the device. A core dielectric layer is formed in the core region (510). A barrier layer is deposited and patterned to expose the NMOS devices of the core region (512). The core dielectric layer is removed from the core NMOS devices (514). A high-k dielectric layer is formed (514) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions/devices of the core region and the NMOS and PMOS regions/devices of the I/O region.
摘要翻译： 本发明通过提供在NMOS区内选择性地形成高k电介质层的制造方法来促进半导体制造。 在半导体器件（506）的芯和I / O区域中形成I / O电介质层。 从器件的芯区域去除（508）I / O电介质层。 在芯区域（510）中形成芯介质层。 屏蔽层被沉积并图案化以暴露核心区域（512）的NMOS器件。 从核心NMOS器件（514）去除芯介质层。 在核心和I / O区域上形成高k电介质层（514）。 然后，从核心区域的PMOS区域/器件和I / O区域的NMOS和PMOS区域/器件去除高k电介质层（512）。
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95.发明授权Method for fabricating transistor gate structures and gate dielectrics thereof 有权制造晶体管栅极结构及其栅极电介质的方法公开(公告)号：US07135361B2
公开(公告)日：2006-11-14
申请号：US10734708
申请日：2003-12-11
IPC分类号： H01L21/336
CPC分类号： H01L21/28185 , H01L21/02148 , H01L21/02271 , H01L21/02332 , H01L21/02337 , H01L21/0234 , H01L21/28202 , H01L21/3144 , H01L21/3162 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L21/31691 , H01L29/517 , H01L29/518
摘要： Methods are disclosed for treating deposited gate dielectric materials, in which the deposited dielectric is subjected to one or more non-oxidizing anneals to densify the material, one or more oxidizing anneals to mitigate material defects, and to a nitridation process to introduce nitrogen into the gate dielectric. The annealing may be performed before and/or after the nitridation to mitigate deposition and/or nitridation defects and to densify the material while mitigating formation of unwanted low dielectric constant oxides at the interface between the gate dielectric and the semiconductor substrate.
摘要翻译： 公开了用于处理沉积的栅极电介质材料的方法，其中沉积的电介质经受一个或多个非氧化退火以致密化材料，一个或多个氧化退火以减轻材料缺陷，以及氮化过程以将氮引入 栅电介质。 可以在氮化之前和/或之后进行退火以减轻沉积和/或氮化缺陷并致密材料，同时减轻在栅极电介质和半导体衬底之间的界面处形成不想要的低介电常数氧化物。
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96.发明授权Top surface roughness reduction of high-k dielectric materials using plasma based processes 有权使用基于等离子体工艺的高k介电材料的顶表面粗糙度降低公开(公告)号：US07115530B2
公开(公告)日：2006-10-03
申请号：US10726987
申请日：2003-12-03
IPC分类号： H01L21/31
CPC分类号： H01L21/0234 , C23C16/401 , C23C16/405 , C23C16/56 , H01L21/02175 , H01L21/02181 , H01L21/02194 , H01L21/3105 , H01L21/31053 , H01L21/3143 , H01L21/3144 , H01L21/31604 , H01L21/31645 , H01L21/31691
摘要： A system and method for manufacturing semiconductor devices with dielectric layers having a dielectric constant greater than silicon dioxide includes depositing a dielectric layer on a substrate and subjecting the dielectric layer to a plasma to reduce top surface roughness in the dielectric layer.
摘要翻译： 具有介电常数大于二氧化硅的电介质层的半导体器件的系统和方法包括在基片上沉积电介质层并对介电层进行等离子体以减小电介质层中的顶表面粗糙度。
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97.发明授权Dual work function gate electrodes using doped polysilicon and a metal silicon germanium compound 有权使用掺杂多晶硅和金属硅锗化合物的双功函数栅电极公开(公告)号：US07109077B2
公开(公告)日：2006-09-19
申请号：US10301224
申请日：2002-11-21
IPC分类号： H01L21/8238 , H01L21/3205
CPC分类号： H01L21/28097 , H01L21/823842 , H01L29/4975
摘要： A dielectric layer (50) is formed over a semiconductor (10) that contains a first region (20) and a second region (30). A polysilicon layer is formed over the dielectric layer (50) and over the first region (20) and the second region (30). The polysilicon layer can comprise 0 to 50 atomic percent of germanium. A metal layer is formed over the polysilicon layer and one of the regions and reacted with the underlying polysilicon layer to form a metal silicide or a metal germano silicide. The polysilicon and metal silicide or germano silicide regions are etched to form transistor gate regions (60) and (90) respectively. If desired a cladding layer (100) can be formed above the metal gate structures.
摘要翻译： 在包含第一区域（20）和第二区域（30）的半导体（10）上形成介电层（50）。 在电介质层（50）上并在第一区域（20）和第二区域（30）之上形成多晶硅层。 多晶硅层可以包含0至50原子％的锗。 在多晶硅层和其中一个区域上形成金属层，并与下面的多晶硅层反应形成金属硅化物或金属锗化硅。 蚀刻多晶硅和金属硅化物或锗硅化物区域以分别形成晶体管栅极区域（60）和（90）。 如果需要，可以在金属栅极结构上方形成包覆层（100）。
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公开(公告)号：US07105891B2
公开(公告)日：2006-09-12
申请号：US10195271
申请日：2002-07-15
IPC分类号： H01L29/94
CPC分类号： H01L29/495 , H01L21/28079 , H01L21/823842
摘要： CMOS gate structure with metal gates having differing work functions by texture differences between NMOS and PMOS gates.
摘要翻译： 具有金属栅极的CMOS栅极结构具有由NMOS和PMOS栅极之间的纹理差异而具有不同功函数。
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99.发明授权Refractory metal-based electrodes for work function setting in semiconductor devices 有权用于半导体器件功能设置的耐火金属基电极公开(公告)号：US07098516B2
公开(公告)日：2006-08-29
申请号：US10852523
申请日：2004-05-24
IPC分类号： H01L29/94
CPC分类号： H01L21/823842 , H01L29/4958
摘要： The present invention provides, in one embodiment, a gate structure (100). The gate structure comprises a gate dielectric (105) and a gate (110). The gate dielectric includes a refractory metal and is located over a semiconductor substrate (115). The semiconductor substrate has a conduction band and a valence band. The gate is located over the gate dielectric and includes the refractory metal. The gate has a work function aligned toward the conduction band or the valence band. Other embodiments include an alternative gate structure (200), a method of forming a gate structure (300) for a semiconductor device (301) and a dual gate integrated circuit (400).
摘要翻译： 本发明在一个实施例中提供一种栅极结构（100）。 栅极结构包括栅极电介质（105）和栅极（110）。 栅极电介质包括难熔金属并且位于半导体衬底（115）之上。 半导体衬底具有导带和价带。 栅极位于栅极电介质上方并且包括难熔金属。 栅极具有与导带或价带对准的功函数。 其他实施例包括替代栅极结构（200），形成用于半导体器件（301）的栅极结构（300）和双栅极集成电路（400）的方法。
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100.发明申请Method and system for modifying a gate dielectric stack containing a high-k layer using plasma processing 有权使用等离子体处理修改包含高k层的栅极电介质叠层的方法和系统公开(公告)号：US20060040483A1
公开(公告)日：2006-02-23
申请号：US10920990
申请日：2004-08-18
IPC分类号： H01L21/3205
CPC分类号： H01L21/022 , H01L21/02142 , H01L21/02175 , H01L21/02274 , H01L21/28185 , H01L21/28202 , H01L21/3115 , H01L21/3144 , H01L21/3165 , H01L29/513 , H01L29/517
摘要： A method and system for modifying a gate dielectric stack by exposure to a plasma. The method includes providing the gate dielectric stack having a high-k layer formed on a substrate, generating a plasma from a process gas containing an inert gas and one of an oxygen-containing gas or a nitrogen-containing gas, where the process gas pressure is selected to control the amount of neutral radicals relative to the amount of ionic radicals in the plasma, and modifying the gate dielectric stack by exposing the stack to the plasma.
摘要翻译： 一种用于通过暴露于等离子体来修改栅极电介质叠层的方法和系统。 该方法包括提供具有形成在衬底上的高k层的栅极电介质堆叠，从含有惰性气体和含氧气体或含氮气体中的一种的工艺气体产生等离子体，其中工艺气体压力 被选择为相对于等离子体中的离子基团的量来控制中性自由基的量，以及通过将该叠层暴露于等离子体来修改栅极电介质堆叠。
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