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    Method, system, and device for phase change memory switch wall cell with approximately horizontal electrode contact
    92.
    发明授权
    Method, system, and device for phase change memory switch wall cell with approximately horizontal electrode contact 有权
    相变存储器开关壁单元的方法，系统和装置，具有大致水平的电极接触

    公开(公告)号：US08976570B2

    公开(公告)日：2015-03-10

    申请号：US14094532

    申请日：2013-12-02

    Applicant: Micron Technology, Inc.

    Inventor： Fabio Pellizzer ,  Innocenzo Tortorelli

    IPC: G11C11/00 ,  H01L45/00 ,  G11C13/00 ,  H01L27/24

    CPC classification number: H01L45/1253 ,  G11C13/0004 ,  G11C13/003 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141

    Abstract: Embodiments disclosed herein may include depositing a storage component material over and/or in a trench in a dielectric material, including depositing the storage component material on approximately vertical walls of the trench and a bottom of the trench. Embodiments may also include etching the storage component material so that at least a portion of the storage component material remains on the approximately vertical walls and the bottom of the trench, wherein the trench is contacting an electrode and a selector such that storage component material on the bottom of the trench contacts the electrode.

    Abstract translation: 本文公开的实施例可以包括在介电材料中的和/或沟槽中沉积存储部件材料，包括在沟槽的大致竖直的壁上和沟槽的底部沉积存储部件材料。 实施例还可以包括蚀刻存储部件材料，使得存储部件材料的至少一部分保留在大致垂直的壁和沟槽的底部上，其中沟槽与电极和选择器接触，使得存储部件材料 沟槽底部接触电极。

    METHOD, SYSTEM, AND DEVICE FOR PHASE CHANGE MEMORY SWITCH WALL CELL WITH APPROXIMATELY HORIZONTAL ELECTRODE CONTACT
    94.
    发明申请
    METHOD, SYSTEM, AND DEVICE FOR PHASE CHANGE MEMORY SWITCH WALL CELL WITH APPROXIMATELY HORIZONTAL ELECTRODE CONTACT 有权
    用于相位变化的存储器开关壁电路的方法，系统和装置具有大量水平电极接触

    公开(公告)号：US20140085974A1

    公开(公告)日：2014-03-27

    申请号：US14094532

    申请日：2013-12-02

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Fabio Pellizzer ,  Innocenzo Tortorelli

    IPC: H01L45/00 ,  G11C13/00

    CPC classification number: H01L45/1253 ,  G11C13/0004 ,  G11C13/003 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141

    Abstract: Embodiments disclosed herein may include depositing a storage component material over and/or in a trench in a dielectric material, including depositing the storage component material on approximately vertical walls of the trench and a bottom of the trench. Embodiments may also include etching the storage component material so that at least a portion of the storage component material remains on the approximately vertical walls and the bottom of the trench, wherein the trench is contacting an electrode and a selector such that storage component material on the bottom of the trench contacts the electrode.

    Abstract translation: 本文公开的实施例可以包括在介电材料中的和/或沟槽中沉积存储部件材料，包括在沟槽的大致竖直的壁上和沟槽的底部沉积存储部件材料。 实施例还可以包括蚀刻存储部件材料，使得存储部件材料的至少一部分保留在大致垂直的壁和沟槽的底部上，其中沟槽与电极和选择器接触，使得存储部件材料 沟槽底部接触电极。

    WRITE LATENCY AND ENERGY USING ASYMMETRIC CELL DESIGN
    95.
    发明申请
    WRITE LATENCY AND ENERGY USING ASYMMETRIC CELL DESIGN 有权

    公开(公告)号：US20250118372A1

    公开(公告)日：2025-04-10

    申请号：US18913710

    申请日：2024-10-11

    Applicant: Micron Technology, Inc.

    Inventor： Mattia Robustelli ,  Innocenzo Tortorelli

    IPC: G11C16/10 ,  G11C16/22 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32 ,  G11C16/34

    Abstract: Methods, systems, and devices for improving write latency and energy using asymmetric cell design are described. A memory device may implement a programming scheme that uses low programming pulses based on an asymmetric memory cell design. For example, the asymmetric memory cells may have electrodes with different contact areas (e.g., widths) and may accordingly be biased to a desired polarity (e.g., negative biased or positive biased) for programming operations. That is, the asymmetric memory cell design may enable an asymmetric read window budget. For example, an asymmetric memory cell may be polarity biased, supporting programming operations for logic states based on the polarity bias.

    ANALOG STORAGE USING MEMORY DEVICE
    96.
    发明申请
    ANALOG STORAGE USING MEMORY DEVICE 有权

    公开(公告)号：US20240420786A1

    公开(公告)日：2024-12-19

    申请号：US18819191

    申请日：2024-08-29

    Applicant: Micron Technology, Inc.

    Inventor： Mattia Boniardi ,  Innocenzo Tortorelli

    IPC: G11C27/00 ,  G06N3/065 ,  G06N3/08

    Abstract: Methods, systems, and devices for analog storing information are described herein. Such methods, systems and devices are suitable for synaptic weight storage in electronic neuro-biological mimicking architectures. A memory device may include a plurality of memory cells each respective memory cell in the plurality of memory cells with a respective programming sensitivity different from the respective programming sensitivity of other memory cells in the plurality. Memory cells may be provided on different decks of a multi-deck memory array. A storage element material of a respective memory cell may have a thickness and/or a composition different from another thickness or composition of a respective storage element material of another respective memory cell on a different deck in the multi-deck memory array. The memory device may further include reading circuitry configured to analogically read respective information programmed in the respective memory cells and to provide an output based on a combination of the respective information analogically read from the respective memory cells.

    READING A MULTI-LEVEL MEMORY CELL
    98.
    发明公开
    READING A MULTI-LEVEL MEMORY CELL 审中-公开

    公开(公告)号：US20240321347A1

    公开(公告)日：2024-09-26

    申请号：US18643126

    申请日：2024-04-23

    Applicant: Micron Technology, Inc.

    Inventor： Mattia Robustelli ,  Fabio Pellizzer ,  Innocenzo Tortorelli ,  Agostino Pirovano

    IPC: G11C11/56 ,  G11C7/10

    CPC classification number: G11C11/56 ,  G11C7/1051 ,  G11C7/1096

    Abstract: Methods, systems, and devices for reading a multi-level memory cell are described. The memory cell may be configured to store three or more logic states. The memory device may apply a first read voltage to a memory cell to determine a logic state stored by the memory cell. The memory device may determine whether a first snapback event occurred and apply a second read voltage based on determining that the first snapback event failed to occur based on applying the first read voltage. The memory device may determine whether a second snapback event occurred and determine the logic state based on whether the first snapback event or the second snapback event occurred.

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