公开(公告)号：US20050003563A1

公开(公告)日：2005-01-06

申请号：US10849148

申请日：2004-05-20

申请人： Shinichi Fukada

发明人： Shinichi Fukada

IPC分类号： H01L27/105 ,  H01L21/00 ,  H01L21/8246 ,  H01L27/10

CPC分类号： H01L27/101

摘要： The invention provides a method for manufacturing a semiconductor device by which product performance and working efficiency can be improved while increasing a capacitor area of cross-point FeRAM. By using a first mask formed on a lower electrode layer forming film, a lower electrode is formed and processed and the lower electrode 2A can be exposed on a first insulating layer. By using a second mask formed on an upper electrode supporting layer forming film, a ferroelectric layer and an upper electrode supporting layer can be formed and processed and the upper electrode supporting layer can be exposed on a second insulating layer.

摘要翻译： 本发明提供一种用于制造半导体器件的方法，通过该方法可以在增加交叉点FeRAM的电容器面积的同时提高产品性能和工作效率。 通过使用形成在下电极层形成膜上的第一掩模，形成并处理下电极，并将下电极2A暴露在第一绝缘层上。 通过使用形成在上电极支撑层形成膜上的第二掩模，可以形成和处理铁电层和上电极支撑层，并且可以在第二绝缘层上暴露上电极支撑层。

公开(公告)号：US06774020B2

公开(公告)日：2004-08-10

申请号：US10355116

申请日：2003-01-31

申请人： Shinichi Fukada ,  Kazuo Nojiri ,  Takashi Yunogami ,  Shoji Hotta ,  Hideo Aoki ,  Takayuki Oshima ,  Nobuyoshi Kobayashi

发明人： Shinichi Fukada ,  Kazuo Nojiri ,  Takashi Yunogami ,  Shoji Hotta ,  Hideo Aoki ,  Takayuki Oshima ,  Nobuyoshi Kobayashi

IPC分类号： H01L2120

CPC分类号： H01L21/76874 ,  H01L21/76804 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76829 ,  H01L21/76843 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

摘要： Insulating films 34 through 38 (of which insulating films 34, 36, 38 are silicon nitride films and insulating films 35, 38 are silicon oxide films) are sequentially formed on the wires 33 of the fourth wiring layer and groove pattern 40 is transferred into the insulating film 38 by means of photolithography. An anti-reflection film 41 is formed to fill the grooves 40 of the insulating film 38 and then a resist film 42 carrying a hole pattern 43 is formed. The films are subjected to an etching operation in the presence of the resist film 42 to transfer the hole pattern into the insulating films 38, 37, 36 and part of the insulating film 35. Subsequently, the resist film 42 and the anti-reflection film 41 are removed and the groove pattern 40 and the hole pattern 43 are transferred respectively into the insulating film 37 and the insulating film 35 by using the insulating film 38 as mask.

摘要翻译： 绝缘膜34至38（其绝缘膜34,36,38是氮化硅膜和绝缘膜35,38是氧化硅膜）依次形成在第四布线层的布线33上，并将凹槽图案40转移到 绝缘膜38。 形成防反射膜41以填充绝缘膜38的槽40，然后形成承载孔图案43的抗蚀剂膜42。 在存在抗蚀剂膜42的情况下对膜进行蚀刻操作，以将孔图案转印到绝缘膜38,37,36和绝缘膜35的一部分中。随后，将抗蚀剂膜42和抗反射膜 41，并且通过使用绝缘膜38作为掩模将槽图案40和孔图案43分别转印到绝缘膜37和绝缘膜35中。

公开(公告)号：US06528400B2

公开(公告)日：2003-03-04

申请号：US09998649

申请日：2001-12-03

申请人： Shinichi Fukada ,  Kazuo Nojiri ,  Takashi Yunogami ,  Shoji Hotta ,  Hideo Aoki ,  Takayuki Oshima ,  Nobuyoshi Kobayashi

发明人： Shinichi Fukada ,  Kazuo Nojiri ,  Takashi Yunogami ,  Shoji Hotta ,  Hideo Aoki ,  Takayuki Oshima ,  Nobuyoshi Kobayashi

IPC分类号： H01L2120

CPC分类号： H01L21/76874 ,  H01L21/76804 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76829 ,  H01L21/76843 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

摘要： Insulating films 34 through 38 (of which insulating films 34, 36, 38 are silicon nitride films and insulating films 35, 38 are silicon oxide films) are sequentially formed on the wires 33 of the fourth wiring layer and groove pattern 40 is transferred into the insulating film 38 by means of photolithography. An anti-reflection film 41 is formed to fill the grooves 40 of the insulating film 38 and then a resist film 42 carrying a hole pattern 43 is formed. The films are subjected to an etching operation in the presence of the resist film 42 to transfer the hole pattern into the insulating films 38, 37, 36 and part of the insulating film 35. Subsequently, the resist film 42 and the anti-reflection film 41 are removed and the groove pattern 40 and the hole pattern 43 are transferred respectively into the insulating film 37 and the insulating film 35 by using the insulating film 38 as mask.

公开(公告)号：US06479899B1

公开(公告)日：2002-11-12

申请号：US09051978

申请日：1998-04-24

申请人： Takuya Fukuda ,  Nobuyoshi Kobayashi ,  Yoshitaka Nakamura ,  Masayoshi Saito ,  Shinichi Fukada ,  Yoshifumi Kawamoto

发明人： Takuya Fukuda ,  Nobuyoshi Kobayashi ,  Yoshitaka Nakamura ,  Masayoshi Saito ,  Shinichi Fukada ,  Yoshifumi Kawamoto

IPC分类号： H01L2348

CPC分类号： H01L27/10808 ,  H01L27/108

摘要： The new structure of a memory cell which enables avoiding the problem of a step without increasing the number of processes, the structure of a semiconductor integrated circuit in which a common part of the same substrate in a manufacturing process is increased and the structure of the semiconductor integrated circuit which allows measures for environment obstacles without increasing the number of processes are disclosed. Memory cell structure in which a capacitor is formed in the uppermost layer of plural metal wiring layers by connecting the storage node of the capacitor to a diffusion layer via plugs and pads is adopted. It is desirable that a dielectric film formed in a metal wiring layer under the uppermost layer and a supplementary capacitor composed of a storage node and a plate electrode are connected to the capacitor. It is also desirable that the plate electrode of the capacitor covers the chip.

公开(公告)号：US06300206B1

公开(公告)日：2001-10-09

申请号：US09486899

申请日：2000-03-03

申请人： Shinichi Fukada ,  Naotaka Hashimoto ,  Masanori Kojima ,  Hiroshi Momiji ,  Hiromi Abe ,  Masayuki Suzuki

发明人： Shinichi Fukada ,  Naotaka Hashimoto ,  Masanori Kojima ,  Hiroshi Momiji ,  Hiromi Abe ,  Masayuki Suzuki

IPC分类号： H01L21331

CPC分类号： H01L29/6659 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/1083

摘要： A implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

摘要翻译： 用于形成源极和漏极区域（S和D）的掺杂剂离子的注入步骤被划分为用于与阱区域（3）形成ap / n结的掺杂剂离子的一次注入，并且一次注入掺杂剂离子 不影响源极和漏极区域（S和D）之间的p / n结的位置以及具有浅的注入深度和大的注入量的阱区域。 在对掺杂剂进行激活热处理之后，将源极/漏极区域的表面制成硅化钴12，使得源极/漏极区域（S和D）可以具有低电阻，并且ap / n结泄漏可以 减少

公开(公告)号：US6000350A

公开(公告)日：1999-12-14

申请号：US709410

申请日：1996-09-06

申请人： Mikio Koike ,  Chiyo Suzuki ,  Shinichi Fuchigami ,  Akiyoshi Sasano ,  Shinichi Fukada

发明人： Mikio Koike ,  Chiyo Suzuki ,  Shinichi Fuchigami ,  Akiyoshi Sasano ,  Shinichi Fukada

IPC分类号： D05B19/10 ,  D05B21/00 ,  D05C5/06 ,  D05C13/02 ,  D05C5/02

CPC分类号： D05B19/10

摘要： An embroidering position setting device and method of operation thereof for an embroidering sewing machine are described. The embroidering sewing machine is capable of storing pattern data in a memory for a plurality of embroidery patterns which can be selectively read out to operate a stitch forming device to form the stitches of a selected pattern or patterns on a cloth to be stitched. An embroidering frame has a cloth extended thereon to be embroidered and is connected to an X-Y drive mechanism, said cloth having a mark located at an optional position for representing a reference embroidering position of the cloth. Jog keys are selectively operated to operate said X-Y drive mechanism thereby to shift said embroidering frame so that said reference embroidering position mark of the cloth may be located at the position under said machine needle in vertical alignment therewith. The position register key is operated to store said position of the reference embroidering position mark in an embroidering position memory as the reference embroidering position data. This position of the reference embroidering position mark is indicated together with crossed lines on a display which is operative in response to operation of said position register key. A pattern selecting device is then operated to select at least one of the embroidery patterns from said pattern memory, said selected embroidery pattern being stored in a memory (RAM) and being simultaneously indicated on said display with the center thereof being located at the center of said crossed lines.

摘要翻译： 描述了一种用于刺绣缝纫机的绣花位置设定装置及其操作方法。 刺绣缝纫机能够将图案数据存储在用于多个刺绣图案的存储器中，可以选择性地读出以操作线圈形成装置，以在待缝合的布上形成所选择的图案或图案的线迹。 刺绣框架上有一个布在其上的绣花布，并连接到一个X-Y驱动机构上，所述的布具有位于可选位置的标记，用于表示布的参考刺绣位置。 选择性地操作点动键以操作所述X-Y驱动机构，从而移动所述绣花框架，使得布的所述参考刺绣位置标记可以位于所述机针下方与其垂直对准的位置处。 操作位置记录键将参考刺绣位置标记的所述位置存储在绣花位置存储器中作为参考绣花位置数据。 参考刺绣位置标记的该位置与显示器上的交叉线一起指示，该显示器响应于所述位置记录键的操作而可操作。 然后操作图案选择装置以从所述图案存储器中选择至少一个刺绣图案，所述选择的刺绣图案存储在存储器（RAM）中，并且同时在所述显示器上指示其中心位于 说交叉线。

公开(公告)号：US5019891A

公开(公告)日：1991-05-28

申请号：US296003

申请日：1989-01-12

申请人： Jin Onuki ,  Yasushi Koubuchi ,  Shinichi Fukada ,  Katuhiko Shiota ,  Kunio Miyazaki ,  Tatsuo Itagaki ,  Genji Taki

发明人： Jin Onuki ,  Yasushi Koubuchi ,  Shinichi Fukada ,  Katuhiko Shiota ,  Kunio Miyazaki ,  Tatsuo Itagaki ,  Genji Taki

IPC分类号： H01L21/285 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L21/76886 ,  H01L21/28518 ,  H01L21/32136 ,  H01L21/76888 ,  H01L23/53219 ,  H01L23/53223 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/01047 ,  H01L2924/10253 ,  Y10T428/12528 ,  Y10T428/12611 ,  Y10T428/12625

摘要： A semiconductor device and the method of fabricating the semiconductor device include a semiconductor substrate and a plurality of conductor films formed on the substrate. Each of the conductor films is made of aluminum alloy including at least one element selected from palladium and platinum and, more preferably, further including at least one element selected from lithium, beryllium, magnesium, manganese, iron, cobalt, nickel, copper, lanthanum, cerium, chromium hafnium, zirconium, cadmium, titanium, tungsten, vanadium, tantalum, and niobium, with a protective film which includes oxide of the selected one of palladium and platinum being formed on the side wall of the conductor film.