公开(公告)号：US08524599B2

公开(公告)日：2013-09-03

申请号：US13050725

申请日：2011-03-17

申请人： Sanh D. Tang ,  Scott E. Sills ,  Whitney L. West ,  Rob B. Goodwin ,  Nishant Sinha

发明人： Sanh D. Tang ,  Scott E. Sills ,  Whitney L. West ,  Rob B. Goodwin ,  Nishant Sinha

IPC分类号： H01L21/4763

CPC分类号： H01L45/1266 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76877 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/53247 ,  H01L23/53252 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the first conductive material. The methods enable formation of silver containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed.

摘要翻译： 形成用于半导体结构和存储单元的导电元件例如互连和电极的方法。 所述方法包括在至少一个开口的一部分中形成第一导电材料和第二导电材料，所述第二导电材料包括银，并且执行抛光工艺以用至少一个第一和第二导电材料填充所述至少一个开口。 可以进行退火处理以形成银和第一导电材料的混合物或合金。 该方法能够形成具有减小的尺寸（例如，小于约20nm）的含银导电元件。 所得的导电元件具有所需的电阻率。 所述方法可以用于例如形成用于电连接有源器件并形成用于存储器单元的电极的互连。 还公开了一种半导体结构和包括这种导电结构的存储单元。

公开(公告)号：US08446767B2

公开(公告)日：2013-05-21

申请号：US12829860

申请日：2010-07-02

申请人： Sanh D. Tang ,  Nishant Sinha

发明人： Sanh D. Tang ,  Nishant Sinha

IPC分类号： G11C16/04

CPC分类号： H01L27/11551 ,  G11C16/0483 ,  H01L27/11578

摘要： Memories and their formation are disclosed. One such memory has first and second memory cells at a first vertical level of the memory, first and second memory cells at a second vertical level of the memory, a first data line is selectively coupled to the first memory cells at the first and second vertical levels, and a second data line over the first data line is selectively coupled to the second memory cells at the first and second vertical levels.

摘要翻译： 记忆及其形成被披露。 一个这样的存储器具有位于存储器的第一垂直级的第一和第二存储器单元，位于存储器的第二垂直级的第一和第二存储器单元，第一数据线选择性地耦合到第一和第二垂直的第一存储器单元 电平和第一数据线上的第二数据线在第一和第二垂直电平选择性地耦合到第二存储器单元。

公开(公告)号：US08435904B2

公开(公告)日：2013-05-07

申请号：US12850441

申请日：2010-08-04

申请人： Nishant Sinha ,  Gurtej S. Sandhu ,  Joseph N. Greeley

发明人： Nishant Sinha ,  Gurtej S. Sandhu ,  Joseph N. Greeley

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/31116 ,  H01L21/76229 ,  H01L21/823412 ,  H01L21/823481 ,  H01L27/11521 ,  H01L29/7846 ,  Y10S438/911

摘要： A method of substantially uniformly removing silicon oxide is disclosed. The silicon oxide to be removed includes at least one cavity therein or more than one density or strain therein. The silicon oxide having the at least one cavity or more than one density or strain is exposed to a gaseous mixture of NH3 and HF and heated, to substantially uniformly remove the silicon oxide. A method of removing an exposed sacrificial layer without substantially removing exposed isolation regions using the gaseous mixture of NH3 and HF and heat is also disclosed, as is an intermediate semiconductor device structure that includes a semiconductor substrate, a sacrificial layer overlying the semiconductor substrate, a diffusion barrier overlying the sacrificial layer, and exposed isolation regions.

摘要翻译： 公开了一种基本均匀地去除氧化硅的方法。 要除去的氧化硅包括其中至少一个空腔或其中的多于一个密度或应变。 将具有至少一个空腔或多于一个密度或应变的氧化硅暴露于NH 3和HF的气体混合物并加热，以基本均匀地除去氧化硅。 还公开了使用NH 3和HF的气体混合物和热量基本上去除暴露的隔离区域去除暴露的牺牲层的方法，中间半导体器件结构包括半导体衬底，覆盖半导体衬底的牺牲层， 覆盖牺牲层的扩散阻挡层和暴露的隔离区域。

公开(公告)号：US08389385B2

公开(公告)日：2013-03-05

申请号：US13088863

申请日：2011-04-18

申请人： Nishant Sinha ,  Gurtej S. Sandhu ,  John Smythe

发明人： Nishant Sinha ,  Gurtej S. Sandhu ,  John Smythe

IPC分类号： H01L21/00

CPC分类号： H01L21/76254

摘要： Electronic apparatus, systems, and methods include a semiconductor layer bonded to a bulk region of a wafer or a substrate, in which the semiconductor layer can be bonded to the bulk region using electromagnetic radiation. Additional apparatus, systems, and methods are disclosed.

摘要翻译： 电子设备，系统和方法包括结合到晶片或基板的主体区域的半导体层，其中半导体层可以使用电磁辐射结合到主体区域。 公开了附加装置，系统和方法。

公开(公告)号：US20130003303A1

公开(公告)日：2013-01-03

申请号：US13612337

申请日：2012-09-12

申请人： Joseph T. Lindgren ,  Warren M. Farnworth ,  William M. Hiatt ,  Nishant Sinha

发明人： Joseph T. Lindgren ,  Warren M. Farnworth ,  William M. Hiatt ,  Nishant Sinha

IPC分类号： H05K7/20

CPC分类号： H01L23/367 ,  H01L23/427 ,  H01L24/31 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/10158 ,  H01L2924/19041 ,  H01L2224/0401

摘要： Microelectronic devices with improved heat dissipation, methods of making microelectronic devices, and methods of cooling microelectronic devices are disclosed herein. In one embodiment, the microelectronic device includes a microelectronic substrate having a first surface, a second surface facing opposite from the first surface, and a plurality of active devices at least proximate to the first surface. The second surface has a plurality of heat transfer surface features that increase the surface area of the second surface. In another embodiment, an enclosure having a heat sink and a single or multi-phase thermal conductor can be positioned adjacent to the second surface to transfer heat from the active devices.

摘要翻译： 本文公开了具有改善的散热的微电子器件，制造微电子器件的方法以及冷却微电子器件的方法。 在一个实施例中，微电子器件包括具有第一表面，与第一表面相对的第二表面的微电子衬底以及至少靠近第一表面的多个有源器件。 第二表面具有增加第二表面的表面积的多个传热表面特征。 在另一个实施例中，具有散热器和单相或多相热导体的外壳可以邻近第二表面定位以传递来自有源器件的热量。

公开(公告)号：US08317930B2

公开(公告)日：2012-11-27

申请号：US13179915

申请日：2011-07-11

申请人： Nishant Sinha

发明人： Nishant Sinha

IPC分类号： B08B3/10

CPC分类号： H01L21/67057 ,  B08B3/04 ,  B08B7/00 ,  H01L21/67086 ,  Y10T137/206 ,  Y10T428/24521

摘要： Methods and apparatus for cleaning a substrate (e.g., wafer) in the fabrication of semiconductor devices utilizing electrorheological (ER) and magnetorheological (MR) fluids to remove contaminant residual particles from the substrate surface are provided.

摘要翻译： 提供了使用电粘滞性（ER）和磁流变（MR）流体制造半导体器件中的衬底（例如，晶片）以从衬底表面去除污染物残留颗粒的方法和装置。

公开(公告)号：US08232206B2

公开(公告)日：2012-07-31

申请号：US12751786

申请日：2010-03-31

申请人： Nishant Sinha ,  Dinesh Chopra ,  Fred D. Fishburn

发明人： Nishant Sinha ,  Dinesh Chopra ,  Fred D. Fishburn

IPC分类号： H01L21/44

CPC分类号： H01L21/288 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76879 ,  H01L23/522 ,  H01L27/10855 ,  H01L27/10888 ,  H01L2924/0002 ,  H01L2924/00

摘要： Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be formed to have a dummy structure thereover with a surface suitable for electroless plating, and to also have a digit line thereover having about the same height as the dummy structure. A layer can be formed over the dummy structure and digit line, and openings can be formed through the layer to the upper surfaces of the dummy structure and digit line. Subsequently, a conductive material can be electroless plated within the openings to form electrical contacts within the openings. The opening extending to the dummy structure can pass through a capacitor electrode, and accordingly the conductive material formed within such opening can be utilized to form electrical contact to the capacitor electrode.

摘要翻译： 可以利用无电镀形成与半导体衬底相关的电互连。 例如，半导体基板可以形成为具有适合于化学镀的表面的虚拟结构，并且还具有与虚拟结构大致相同的高度的数字线。 可以在虚拟结构和数字线上形成层，并且可以通过该层到虚拟结构和数字线的上表面形成开口。 随后，导电材料可以在开口内无电镀，以在开口内形成电接触。 延伸到虚拟结构的开口可以通过电容器电极，因此形成在该开口内的导电材料可用于与电容器电极形成电接触。

公开(公告)号：US08148263B2

公开(公告)日：2012-04-03

申请号：US12648864

申请日：2009-12-29

申请人： Nishant Sinha

发明人： Nishant Sinha

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L23/49827 ,  H01L21/76898 ,  H01L23/481 ,  H01L2224/02372 ,  H01L2224/0557 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming conductive vias in a substrate of a semiconductor device component includes forming one or more holes, or apertures or cavities, in the substrate so as to extend only partially through the substrate. A barrier layer, such as an insulative layer, may be formed on surfaces of each hole. Surfaces within each hole may be coated with a seed layer, which facilitates adhesion of conductive material within each hole. Conductive material is introduced into each hole. Introduction of the conductive material may be effected by deposition or plating. Alternatively, conductive material in the form of solder may be introduced into each hole.

摘要翻译： 在半导体器件部件的衬底中形成导电通孔的方法包括在衬底中形成一个或多个孔或孔或空腔，以便仅部分延伸穿过衬底。 可以在每个孔的表面上形成诸如绝缘层的阻挡层。 每个孔中的表面可以涂覆有种子层，这有助于在每个孔内粘附导电材料。 将导电材料引入每个孔中。 导电材料的引入可以通过沉积或电镀来实现。 或者，可以将每种孔中引入焊料形式的导电材料。

公开(公告)号：US08131768B2

公开(公告)日：2012-03-06

申请号：US12331344

申请日：2008-12-09

申请人： Nishant Sinha

发明人： Nishant Sinha

IPC分类号： G06F7/00

CPC分类号： G06F8/433

摘要： Systems and methods are disclosed for analyzing data-flow using program expressions or terms by extracting a control flow graph node from a work list; merging symbolic term values at join nodes; performing simplification of term values using rewriting logic; determining successors of the graph node to which data must be propagated; and updating symbolic data for elements of the successors.

摘要翻译： 公开了用于使用程序表达或术语分析数据流的系统和方法，通过从工作列表中提取控制流图节点; 在连接节点合并符号术语值; 使用重写逻辑执行术语值的简化; 确定必须传播数据的图形节点的后继; 并更新后续元素元素的符号数据。

公开(公告)号：US20110272754A1

公开(公告)日：2011-11-10

申请号：US12776965

申请日：2010-05-10

申请人： Sanh D. Tang ,  John Zahurak ,  Siddartha Kondoju ,  Haitao Liu ,  Nishant Sinha

发明人： Sanh D. Tang ,  John Zahurak ,  Siddartha Kondoju ,  Haitao Liu ,  Nishant Sinha

IPC分类号： H01L29/788 ,  H01L21/336 ,  H01L21/8229 ,  H01L21/76

CPC分类号： H01L27/11293 ,  H01L21/823885 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11206 ,  H01L27/11517 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11563 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

摘要： Memories and their formation are disclosed. One such memory has a first array of first memory cells extending in a first direction from a first surface of a semiconductor. A second array of second memory cells extends in a second direction, opposite to the first direction, from a second surface of the semiconductor. Both arrays may be non-volatile memory arrays. For example, one of the memory arrays may be a NAND flash memory array, while the other may be a one-time-programmable memory array.

摘要翻译： 记忆及其形成被披露。 一个这样的存储器具有从半导体的第一表面沿第一方向延伸的第一存储单元阵列。 第二阵列的第二存储单元从与半导体的第二表面在第二方向相反的第二方向延伸。 两个阵列可以是非易失性存储器阵列。 例如，存储器阵列之一可以是NAND快闪存储器阵列，而另一个可以是一次可编程存储器阵列。