公开(公告)号：US20160371157A1

公开(公告)日：2016-12-22

申请号：US15182328

申请日：2016-06-14

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Wietfeldt ,  George Wiley

IPC: G06F11/16 ,  G06F1/32

CPC classification number: G06F11/0766 ,  G06F1/3296 ,  G06F11/1604 ,  G06F11/162 ,  G06F13/4282

Abstract: A bit-by-bit error correction technique is disclosed that divides each bit transmission into an acknowledgment phase, an error correction phase, and a transmission phase.

Abstract translation: 公开了一种逐位错误校正技术，其将每个位传输划分为确认阶段，纠错阶段和传输阶段。

公开(公告)号：US20160246570A1

公开(公告)日：2016-08-25

申请号：US14631078

申请日：2015-02-25

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  George Alan Wiley

IPC: G06F5/16 ,  G06F5/06 ,  G06F1/12 ,  G06F13/40 ,  G06F13/16

CPC classification number: G06F5/16 ,  G06F1/12 ,  G06F5/065 ,  G06F13/1673 ,  G06F13/385 ,  G06F13/4022

Abstract: A line multiplexed UART interface is provided that multiplexes a UART transmit and CTS functions on a transmit pin and that multiplexes a UART receive and RTS functions on a receive pin. In this fashion, the conventional need for an additional RTS pin and an additional CTS pin is obviated such that the line multiplexed UART interface uses just the transmit pin and the receive pin.

Abstract translation: 提供了一种线路复用UART接口，可在发送引脚上复用UART发送和CTS功能，并在接收引脚上复用UART接收和RTS功能。 以这种方式，消除了额外的RTS引脚和附加CTS引脚的常规需求，使得线路复用UART接口仅使用发送引脚和接收引脚。

公开(公告)号：US20160098073A1

公开(公告)日：2016-04-07

申请号：US14864586

申请日：2015-09-24

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Wietfeldt ,  James Panian

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3243 ,  G06F13/4286 ,  G06F13/4295

Abstract: A dual-data-rate interface is provided that includes a transmitter driving a transmit pin coupled to a receive pin of a receiver. The receiver drives its receive pin with cycles of a fetch clock. The transmitter responds to each edge of the fetch clock by transmitting a bit over the transmit pin to the receiver.

Abstract translation: 提供了一种双数据速率接口，其包括驱动耦合到接收器的接收引脚的发送引脚的发射器。 接收器通过提取时钟周期驱动其接收引脚。 发送器通过将发送引脚上的位发送到接收器来响应获取时钟的每个边沿。

公开(公告)号：US20160077995A1

公开(公告)日：2016-03-17

申请号：US14850809

申请日：2015-09-10

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  James Lionel Panian ,  Radu Pitigoi-Aron

IPC: G06F13/42 ,  G06F1/10

CPC classification number: G06F13/4221 ,  G06F1/10 ,  G06F13/385

Abstract: A virtual GPIO interface is provided that receives a transmit set of GPIO signals from a processor. The virtual GPIO interface transmits a portion of the transmit set of GPIO signals over GPIO pins in a conventional fashion. However, the virtual GPIO interface provides a remaining portion of the transmit set of GPIO signals to a finite state machine that serializes the GPIO signals in the remaining portion into frames of virtual GPIO signals. A modified UART interface transmits the frames over a UART transmit pin responsive to cycles of a UART oversampling clock.

Abstract translation: 提供了一个从处理器接收GPIO信号发送组件的虚拟GPIO接口。 虚拟GPIO接口以传统方式通过GPIO引脚传输GPIO信号发送组的一部分。 然而，虚拟GPIO接口将GPIO信号发送组的剩余部分提供给有限状态机，将剩余部分中的GPIO信号序列化为虚拟GPIO信号帧。 一个经过修改的UART接口可以响应UART过采样时钟的周期，通过UART发送引脚发送帧。

公开(公告)号：US09252997B1

公开(公告)日：2016-02-02

申请号：US14328556

申请日：2014-07-10

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Timothy Mowry Hollis

IPC: H04L25/49 ,  H04L27/06 ,  H04L25/06

CPC classification number: H04L25/4927 ,  H04L25/0292 ,  H04L25/0298 ,  H04L25/06 ,  H04L25/4915 ,  H04L25/4917 ,  H04L27/06

Abstract: High-speed data links between a processor and off-chip DRAM utilizes pulse-amplitude-modulation (PAM) signaling to increase data rate for a given bandwidth and resource budget in SoCs. However, the termination resistor used in the transmission line interface between processor and DRAM consumes large amounts of power during PAM signaling. By adding a biasing source between Ground and the termination resistor, the “floor voltage” that the termination resistor uses as a reference for determining signaling levels may be raised. Raising the floor voltage reduces the amount of voltage across the termination resistor and reduces power consumption accordingly. The biasing source is adjusted to various increments of the maximum amplitude of the PAM signaling. A floor voltage of one-half of the maximum amplitude of PAM signaling produces minimum power consumption in the receiver. Additionally, data inversion pre-coding may be concatenated with the floor voltage adjustment to further maximize power savings of the interface.

Abstract translation: 处理器和片外DRAM之间的高速数据链路利用脉冲幅度调制（PAM）信号来提高SoC中给定带宽和资源预算的数据速率。 然而，处理器和DRAM之间的传输线接口中使用的终端电阻在PAM信令期间消耗大量的功率。 通过在接地端子和终端电阻之间增加一个偏压源，终端电阻器用作确定信号电平的基准的“底电压”可能会提高。 提高地板电压会降低终端电阻两端的电压，从而降低功耗。 偏置源被调整到PAM信号的最大幅度的各种增量。 PAM信令的最大幅度的一半的地电压在接收机中产生最小功耗。 另外，数据反转预编码可以与底层电压调整相连接，以进一步最大化接口的功率节省。

公开(公告)号：US12283961B2

公开(公告)日：2025-04-22

申请号：US18449554

申请日：2023-08-14

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Umesh Srikantiah ,  Richard Dominic Wietfeldt

IPC: H03K5/24 ,  H03K3/037 ,  H03K3/356

Abstract: A clock generation apparatus includes a counter configured to count transitions in a locally generated clock signal when a data signal is received from a 1-wire serial bus, a latch configured to capture an output of the counter and to provide a latched output representative of the transitions counted in the locally generated clock signal while a synchronization pattern is received in the data signal, a flipflop and a comparator configured to drive a decision signal to a first signaling state when the output of the counter matches the latched output and to drive the decision signal to a second signaling state when the output of the counter does not match the latched output. The flipflop has an output that changes signaling state in response to an edge in the decision signal. The counter is reset when the decision signal is driven to the first signaling state.

公开(公告)号：US12248365B2

公开(公告)日：2025-03-11

申请号：US18183833

申请日：2023-03-14

Applicant: QUALCOMM Incorporated

Inventor： Umesh Srikantiah ,  Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  Boris Alpin ,  Francesco Gatta

IPC: G06F11/07 ,  G06F13/42

Abstract: A receiving circuit has a clock generator circuit, a synchronization circuit and a controller. The clock generator circuit is configured to generate a base clock signal with a base frequency. The synchronization circuit is configured to synchronize edges in the base clock signal with edges in a Manchester-encoded data signal received over a serial bus. The controller is configured to detect that a first pulse received from the serial bus has a duration corresponding to a pulse duration defined for a first type of sequence start condition that indicates a first type of transaction during which the Manchester-encoded data signal is received over the serial bus; configure a first timer to expire after a first timeout period; and ignore the first pulse when signaling consistent with the first type of sequence start condition has not been received before the first timer expires.

公开(公告)号：US12124401B2

公开(公告)日：2024-10-22

申请号：US18155499

申请日：2023-01-17

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Umesh Srikantiah ,  Francesco Gatta ,  Richard Dominic Wietfeldt

IPC: G06F13/42 ,  G06F13/24

CPC classification number: G06F13/4295 ,  G06F13/24

Abstract: A data communication apparatus comprises a line driver configured to couple the data communication apparatus to a 1-wire serial bus; and a controller configured to: transmit a plurality of synchronization pulses over the 1-wire serial bus after a sequence start condition (SSC) has been transmitted over the 1-wire serial bus, the plurality of synchronization pulses being configured to synchronize one or more receiving devices coupled to the 1-wire serial bus to an untransmitted transmit clock signal; initiate an interrupt handling procedure when the plurality of synchronization pulses is encoded with a first value; and initiate a read transaction or a write transaction with at least one of the one or more receiving devices coupled to the 1-wire serial bus when the plurality of synchronization pulses is encoded with a second value.

公开(公告)号：US11907154B2

公开(公告)日：2024-02-20

申请号：US17861886

申请日：2022-07-11

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Umesh Srikantiah ,  Francesco Gatta ,  Muhlis Kenan Ozel ,  Richard Dominic Wietfeldt

IPC: G06F13/40 ,  H04L7/00 ,  H04L7/04

CPC classification number: G06F13/4068 ,  H04L7/0066 ,  H04L7/0087 ,  H04L7/042 ,  G06F2213/40

Abstract: A receive clock generated at a receiver coupled to a one-wire bus is synchronized in each clock cycle, permitting reception of a data frame of unlimited length without clock overrun or underrun. A base clock signal provided by an oscillator is passed by a clock gating circuit while the clock gating circuit is enabled. A counter counts positive and negative edges in an output of the clock gating circuit. The clock gating circuit is disabled when an output of the counter indicates a preconfigured maximum count value. An edge synchronization circuit that synchronizes edges in the base clock signal with edges in a data signal received over the one-wire bus ignores edges in the data signal while the counter output has a value that is less than the maximum count value, and resets the counter in response to an edge detected in the data signal received over the one-wire bus.

公开(公告)号：US11847087B2

公开(公告)日：2023-12-19

申请号：US17477250

申请日：2021-09-16

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Radu Pitigoi-Aron ,  Richard Dominic Wietfeldt

IPC: G06F13/42 ,  G06F13/32 ,  G06F13/38

CPC classification number: G06F13/4282 ,  G06F13/32 ,  G06F13/387

Abstract: Systems and methods for chip operation using serial peripheral interface (SPI) with reduced pin options contemplate eliminating the chip select pins, interrupt pins and/or reset pins for host (also referred to as master)-to-device (also referred to as slave) communication links, while preserving the possibility of backward compatibility for legacy devices if desired. The communication link may include a clock line, a host-to-device line, and a device-to-host line. The host may use specific sequences of signals on the clock and host-to-device line to provide start and stop sequence commands, interrupts, or reset commands. By consolidating these commands onto the clock and host-to-device line, pin count may be reduced for portions of the host and slave circuits. Likewise, fewer (or at least shorter potentially) conductive traces may be needed to interconnect the host to the device. Such changes may save cost, make layout design easier, and/or save space within a computing device.