公开(公告)号：US20110260233A1

公开(公告)日：2011-10-27

申请号：US12886421

申请日：2010-09-20

Applicant: Bich-Yen Nguyen ,  Carlos Mazure ,  Richard Ferrant

Inventor： Bich-Yen Nguyen ,  Carlos Mazure ,  Richard Ferrant

IPC: H01L29/788 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L21/823462 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/0705 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/7881

Abstract: The present invention relates to a semiconductor device that has a semiconductor-on-insulator (SeOI) structure, which includes a substrate, an insulating layer such as an oxide layer on the substrate and a semiconductor layer on the insulating layer with a field-effect-transistor (FET) formed in the SeOI structure from the substrate and deposited layers, wherein the FET has a channel region in the substrate, a gate dielectric layer that is made from at least a part of the oxide layer of the SeOI structure; and a gate electrode that is formed at least partially from a part of the semiconductor layer of the SeOI structure. The invention further relates to a method of forming one or more field-effect-transistors or metal-oxide-semiconductor transistors from a semiconductor-on-insulator structure that involves patterning and etching the SeOI structure, forming shallow trench isolations, depositing insulating, metal or semiconductor layers, and removing mask and/or pattern layers.

Abstract translation: 本发明涉及一种具有绝缘体上半导体（SeOI）结构的半导体器件，其包括衬底，绝缘层如衬底上的氧化物层和具有场效应的绝缘层上的半导体层 - 晶体管（FET），其从所述衬底和沉积层形成在所述SeOI结构中，其中所述FET在所述衬底中具有沟道区;栅极介电层，其由所述SeOI结构的所述氧化物层的至少一部分制成; 以及至少部分地由SeOI结构的半导体层的一部分形成的栅电极。 本发明还涉及从绝缘体上半导体结构形成一个或多个场效应晶体管或金属氧化物半导体晶体管的方法，该方法包括图案化和蚀刻SeOI结构，形成浅沟槽隔离，沉积绝缘金属 或半导体层，以及去除掩模和/或图案层。

公开(公告)号：US20110233675A1

公开(公告)日：2011-09-29

申请号：US13039167

申请日：2011-03-02

Applicant: Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

Inventor： Carlos Mazure ,  Richard Ferrant ,  Bich-Yen Nguyen

IPC: H01L27/092 ,  H01L21/28

CPC classification number: H01L27/1104 ,  G11C11/412 ,  H01L21/84 ,  H01L27/1203

Abstract: An SRAM-type memory cell that includes a semiconductor on insulator substrate having a thin film of semiconductor material separated from a base substrate by an insulating layer; and six transistors such as two access transistors, two conduction transistors and two charge transistors arranged so as to form with the conduction transistors two back-coupled inverters. Each of the transistors has a back control gate formed in the base substrate below the channel and able to be biased in order to modulate the threshold voltage of the transistor, with a first back gate line connecting the back control gates of the access transistors to a first potential and a second back gate line connecting the back control gates of the conduction transistors and charge transistors to a second potential. The first and second potentials can be modulated according to the type of cell control operation.

Abstract translation: 一种SRAM型存储单元，包括绝缘体上半导体衬底，其具有通过绝缘层从基底衬底分离的半导体材料薄膜; 以及六个晶体管，例如两个存取晶体管，两个导通晶体管和两个电荷晶体管，其布置成与导通晶体管形成两个反向耦合的反相器。 每个晶体管具有形成在通道下方的基底衬底中的后控制栅极，并且能够被偏置以便调制晶体管的阈值电压，第一背栅极线将存取晶体管的背控制栅极连接到 第一电位和第二背栅极线，其将导通晶体管和电荷晶体管的背控制栅极连接到第二电位。 第一和第二电位可以根据电池控制操作的类型进行调制。

公开(公告)号：US20110134698A1

公开(公告)日：2011-06-09

申请号：US12946135

申请日：2010-11-15

Applicant: Carlos Mazure ,  Richard Ferrant

Inventor： Carlos Mazure ,  Richard Ferrant

IPC: G11C16/04 ,  H01L29/772 ,  H01L21/336

CPC classification number: H01L29/7881 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42336

Abstract: The invention relates to a flash memory cell having a FET transistor with a floating gate on a semiconductor-on-insulator (SOI) substrate composed of a thin film of semiconductor material separated from a base substrate by an insulating buried oxide (BOX) layer, The transistor has in the thin film, a channel, with two control gates, a front control gate located above the floating gate and separated from it by an inter-gate dielectric, and a back control gate located within the base substrate directly under the insulating (BOX) layer and separated from the channel by only the insulating (BOX) layer. The two control gates are designed to be used in combination to perform a cell programming operation. The invention also relates to a memory array made up of a plurality of memory cells according to the first aspect of the invention, which can be in an array of rows and columns, and a method of fabricating such memory cells and memory arrays.

Abstract translation: 本发明涉及一种闪存单元，其具有在绝缘体上绝缘体（SOI）衬底上具有浮置栅极的FET晶体管，该半导体材料由通过绝缘掩埋氧化物（BOX）层从基底衬底分离的半导体材料薄膜构成， 晶体管在薄膜中具有通道，具有两个控制栅极，位于浮置栅极上方的前控制栅极，并通过栅极间电介质与栅极间绝缘体分离，以及位于绝缘子下方的基底衬底内的反控制栅极 （BOX）层，并且仅通过绝缘（BOX）层与沟道分离。 两个控制门被设计成组合使用以执行单元编程操作。 本发明还涉及由根据本发明的第一方面的多个存储单元组成的存储器阵列，其可以是行和列的阵列，以及制造这种存储单元和存储器阵列的方法。

公开(公告)号：US20110134690A1

公开(公告)日：2011-06-09

申请号：US12898230

申请日：2010-10-05

Applicant: Carlos Mazure ,  Richard Ferrant

Inventor： Carlos Mazure ,  Richard Ferrant

IPC: G11C11/34 ,  H01L29/772 ,  H01L21/336

CPC classification number: G11C11/404 ,  G11C2211/4016 ,  H01L27/10802 ,  H01L27/1203 ,  H01L29/42356 ,  H01L29/7841

Abstract: The invention relates to a method of controlling a DRAM memory cell of an FET transistor on a semiconductor-on-insulator substrate that includes a thin film of semiconductor material separated from a base substrate by an insulating layer or BOX layer, the transistor having a channel and two control gates, a front control gate being arranged on top of the channel and separated from the latter by a gate dielectric and a back control gate being arranged in the base substrate and separated from the channel by the insulating layer (BOX). In a cell programming operation, the front control gate and the back control gate are operated jointly by applying a first voltage to the front control gate and a second voltage to the back control gate, with the first voltage being lower in amplitude than the voltage needed to program the cell when no voltage is applied to the back control gate.

Abstract translation: 本发明涉及一种控制绝缘体上半导体衬底上的FET晶体管的DRAM存储单元的方法，该方法包括通过绝缘层或BOX层从基底衬底分离的半导体材料的薄膜，晶体管具有通道 和两个控制栅极，前控制栅极布置在通道的顶部并且由栅介质和背控制栅极分隔开，栅极电介质和背控制栅极被布置在基底衬底中并且通过绝缘层（BOX）与通道分离。 在单元编程操作中，前控制栅极和后控制栅极通过向前控制栅极施加第一电压和向后控制栅极施加第二电压来共同操作，第一电压的幅度低于所需的电压 当没有电压施加到后控制门时对单元进行编程。

公开(公告)号：US07733693B2

公开(公告)日：2010-06-08

申请号：US12082020

申请日：2008-04-08

Applicant: Richard Ferrant ,  Serguei Okhonin ,  Eric Carman ,  Michel Bron

Inventor： Richard Ferrant ,  Serguei Okhonin ,  Eric Carman ,  Michel Bron

IPC: G11C11/34

CPC classification number: G11C11/404 ,  G11C7/18 ,  G11C8/08 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4097 ,  G11C2211/4016 ,  G11C2211/4065 ,  H01L21/84 ,  H01L27/10802 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841

Abstract: There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this aspect of the invention, the memory device and technique for operating that device that minimizes, reduces and/or eliminates the debilitating affects of the charge pumping phenomenon. This embodiment of the present invention employs control signals that minimize, reduce and/or eliminate transitions of the amplitudes and/or polarities. In another embodiment, the present invention is a semiconductor memory device including a memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns. Each semiconductor dynamic random access memory cell includes a transistor having a source region, a drain region, a electrically floating body region disposed between and adjacent to the source region and the drain region, and a gate spaced apart from, and capacitively coupled to, the body region. Each transistor includes a first state representative of a first charge in the body region, and a second data state representative of a second charge in the body region. Further, each row of semiconductor dynamic random access memory cells includes an associated source line which is connected to only the semiconductor dynamic random access memory cells of the associated row.

Abstract translation: 这里描述和说明了许多发明。 在第一方面，本发明涉及一种从数据读取和将数据写入存储器件的存储单元的存储器件和技术。 在这方面，在本发明的这个方面的一个实施例中，用于操作该装置的存储器件和技术使得最小化，减少和/或消除电荷泵送现象的衰弱影响。 本发明的该实施例采用最小化，减少和/或消除幅度和/或极性的转变的控制信号。 在另一个实施例中，本发明是一种包括存储阵列的半导体存储器件，该存储器阵列包括以行和列为矩阵排列的多个半导体动态随机存取存储器单元。 每个半导体动态随机存取存储单元包括晶体管，其具有源极区，漏极区，设置在源极区和漏极区之间且与源极区和漏极区相邻的电浮动体区域，以及与该区域和漏极区域间隔开并电容耦合的栅极 身体区域。 每个晶体管包括代表身体区域中的第一电荷的第一状态和代表身体区域中的第二电荷的第二数据状态。 此外，每排半导体动态随机存取存储器单元包括仅与相关行的半导体动态随机存取存储单元连接的相关源线。

公开(公告)号：US20070069296A1

公开(公告)日：2007-03-29

申请号：US11369194

申请日：2006-03-06

Applicant: Human Park ,  Rainer Leuschner ,  Ulrich Klostermann ,  Richard Ferrant

Inventor： Human Park ,  Rainer Leuschner ,  Ulrich Klostermann ,  Richard Ferrant

IPC: H01L27/12

CPC classification number: H01L27/228 ,  B82Y10/00

Abstract: A cell design and methods for reducing the cell size of cells in high-current devices, such as MRAM, by increasing the effective width of a transistor in the cell to be greater than the actual width of the active area of the cell are described. This permits the cell size to be decreased without decreasing the current that is driven by the transistor. According to the invention, this is achieved by increasing the length of gate portions of one or more transistors within the active area of a cell to increase the effective transistor width. In one embodiment, two transistors, electrically connected in parallel, are used per cell. The two transistors double the effective transistor width within the cell relative to a single transistor design. Such cell designs can be used with a variety of devices, including various types of MRAM and PCRAM.

Abstract translation: 描述了通过将电池中的晶体管的有效宽度增加到大于电池的有效面积的实际宽度来减小大电流器件（例如MRAM）中的电池单元尺寸的电池设计和方法。 这允许在不降低由晶体管驱动的电流的情况下降低电池尺寸。 根据本发明，这通过增加单元的有效区域内的一个或多个晶体管的栅极部分的长度来增加有效晶体管宽度来实现。 在一个实施例中，每个单元使用并联电连接的两个晶体管。 两个晶体管相对于单晶体管设计，使单元内的有效晶体管宽度倍增。 这样的单元设计可以与各种设备一起使用，包括各种类型的MRAM和PCRAM。

公开(公告)号：US07180160B2

公开(公告)日：2007-02-20

申请号：US10903722

申请日：2004-07-30

Applicant: Richard Ferrant ,  Daniel Braun ,  Pascal Louis

Inventor： Richard Ferrant ,  Daniel Braun ,  Pascal Louis

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L27/224

Abstract: A MRAM storage device comprises a substrate, on/above of which a plurality of word lines, a plurality of bit lines, a plurality of memory cells, and a plurality of isolation diodes are provided. Each memory cell forms a resistive cross point of one word line and one bit line, respectively. Each memory cell is connected to one isolation diode such that a unidirectional conductive path is formed from a word line to a bit line via the corresponding memory cell, respectively. The substrate, at least a part of the word lines or at least a part of the bit lines, and the isolation diodes are realized as one common monocrystal semiconductor block.

Abstract translation: MRAM存储设备包括其上/其上提供有多个字线，多个位线，多个存储器单元和多个隔离二极管的衬底。 每个存储单元分别形成一个字线和一个位线的电阻交叉点。 每个存储单元连接到一个隔离二极管，使得单向导电路径分别通过对应的存储单元从字线形成到位线。 基板，字线的至少一部分或位线的至少一部分以及隔离二极管被实现为一个常见的单晶半导体块。

公开(公告)号：US07085156B2

公开(公告)日：2006-08-01

申请号：US11096970

申请日：2005-04-01

Applicant: Richard Ferrant ,  Serguei Okhonin ,  Eric Carman ,  Michel Bron

Inventor： Richard Ferrant ,  Serguei Okhonin ,  Eric Carman ,  Michel Bron

IPC: G11C11/34 ,  G11C7/00

CPC classification number: G11C11/404 ,  G11C7/18 ,  G11C8/08 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4097 ,  G11C2211/4016 ,  G11C2211/4065 ,  H01L21/84 ,  H01L27/10802 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841

Abstract: There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this aspect of the invention, the memory device and technique for operating that device that minimizes, reduces and/or eliminates the debilitating affects of the charge pumping phenomenon. This embodiment of the present invention employs control signals that minimize, reduce and/or eliminate transitions of the amplitudes and/or polarities. In another embodiment, the present invention is a semiconductor memory device including a memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns. Each semiconductor dynamic random access memory cell includes a transistor having a source region, a drain region, a electrically floating body region disposed between and adjacent to the source region and the drain region, and a gate spaced apart from, and capacitively coupled to, the body region. Each transistor includes a first state representative of a first charge in the body region, and a second data state representative of a second charge in the body region. Further, each row of semiconductor dynamic random access memory cells includes an associated source line which is connected to only the semiconductor dynamic random access memory cells of the associated row.

Abstract translation: 这里描述和说明了许多发明。 在第一方面，本发明涉及一种从数据读取和将数据写入存储器件的存储单元的存储器件和技术。 在这方面，在本发明的这个方面的一个实施例中，用于操作该装置的存储器件和技术使得最小化，减少和/或消除电荷泵送现象的衰弱影响。 本发明的该实施例采用最小化，减少和/或消除幅度和/或极性的转变的控制信号。 在另一个实施例中，本发明是一种包括存储阵列的半导体存储器件，该存储器阵列包括以行和列为矩阵排列的多个半导体动态随机存取存储器单元。 每个半导体动态随机存取存储单元包括晶体管，其具有源极区，漏极区，设置在源极区和漏极区之间且与源极区和漏极区相邻的电浮动体区域，以及与该区域和漏极区域间隔开并电容耦合的栅极 身体区域。 每个晶体管包括代表身体区域中的第一电荷的第一状态和代表身体区域中的第二电荷的第二数据状态。 此外，每排半导体动态随机存取存储器单元包括仅与相关行的半导体动态随机存取存储单元连接的相关联的源极线。

公开(公告)号：US20060067112A1

公开(公告)日：2006-03-30

申请号：US10955837

申请日：2004-09-30

Applicant: Richard Ferrant ,  Daniel Braun

Inventor： Richard Ferrant ,  Daniel Braun

IPC: G11C11/14 ,  G11C5/06

CPC classification number: H01L27/228 ,  G11C8/14 ,  G11C11/15 ,  G11C2213/79 ,  H01L29/785

Abstract: A resistive memory cell random access memory device and method for fabrication. In one embodiment, the invention relates to a resistive memory cell random access memory device comprising a plurality of first current lines; a plurality of second current lines; a plurality of third current lines being formed as split current lines; and an array of resistive memory cells arranged in columns defined by said first current lines and rows defined by said third current lines, each resistive memory cell including a resistive memory element and an access transistor connected in series, each memory cell being connected between one of said first current lines and a reference potential, wherein said access transistors being FinFET-type field effect transistors, each one having two independent gates and a common floating body, and wherein each third current line being connected to one of said two independent gates of each one of the access transistors of a row of said array and being connected to one of said two independent gates of each one of the access transistors of an adjacent row of said array. It also relates to a method for its fabrication.

Abstract translation: 一种电阻式存储单元随机存取存储器件及其制造方法。 在一个实施例中，本发明涉及包括多条第一电流线的电阻式存储单元随机存取存储器件; 多条第二电流线; 多条第三电流线被形成为分流电流线; 以及由所述第一电流线限定的列和由所述第三电流线限定的行的电阻性存储单元的阵列，每个电阻性存储单元包括电阻性存储元件和串联连接的存取晶体管，每个存储单元连接在 所述第一电流线和参考电位，其中所述存取晶体管是FinFET型场效应晶体管，每个具有两个独立的栅极和共同的浮动体，并且其中每个第三电流线连接到每个的所述两个独立栅极之一 所述阵列的行的存取晶体管之一并且连接到所述阵列的相邻行的每个存取晶体管的每一个的所述两个独立栅极之一。 它还涉及其制造方法。

公开(公告)号：US20060067103A1

公开(公告)日：2006-03-30

申请号：US10955832

申请日：2004-09-30

Applicant: Richard Ferrant ,  Arkalgud Sitaram

Inventor： Richard Ferrant ,  Arkalgud Sitaram

IPC: G11C11/00

CPC classification number: G11C11/15

Abstract: A configuration of resistive memory cells is disclosed. In one embodiment, the configuration of resistive memory cells comprises a plurality of first current lines; a plurality of second current lines; and a plurality of third current lines. A plurality of resistive memory cells being disposed in a memory matrix form between said first and second current lines, said first current lines defining the columns of said memory matrix form, while said second current lines defining the rows of it, wherein each one of the resistive memory cells being connected to one of said first current lines; a plurality of selection transistors having gates and drain-source paths, each drain-source path of said selection transistors being connected to a multiplicity of the resistive memory cells of a row of said memory matrix, said drain-source paths of different selection transistors being connected to a fourth current line (SL), the gates of said selection transistors of a row of said memory matrix form being connected to one of said third current lines. It further relates to a method for sensing the resistance values of a selected resistive memory cell.

Abstract translation: 公开了一种电阻式存储单元的结构。 在一个实施例中，电阻存储单元的配置包括多条第一电流线; 多条第二电流线; 和多条第三电流线。 多个电阻存储器单元以所述第一和第二电流线之间的存储矩阵形式布置，所述第一电流线限定所述存储矩阵形式的列，而所述第二电流线限定其行，其中每个 电阻存储器单元连接到所述第一电流线之一; 具有栅极和漏极 - 源极路径的多个选择晶体管，所述选择晶体管的每个漏 - 源路径连接到所述存储矩阵的行的多个电阻存储单元，所述不同选择晶体管的所述漏 - 源路径为 连接到第四电流线（SL），所述存储矩阵形式的行的所述选择晶体管的栅极连接到所述第三电流线之一。 本发明还涉及一种用于感测所选择的电阻性存储单元的电阻值的方法。