公开(公告)号：US06391732B1

公开(公告)日：2002-05-21

申请号：US09595061

申请日：2000-06-16

申请人： Subhash Gupta ,  Yelehanka Ramachandramurthy ,  Vijai Kumar Chhagan

发明人： Subhash Gupta ,  Yelehanka Ramachandramurthy ,  Vijai Kumar Chhagan

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/266 ,  H01L21/31116 ,  H01L29/6656 ,  H01L29/7833

摘要： A new method of forming silicon nitride sidewall spacers has been achieved. In addition, a new device profile for a silicon nitride sidewall spacer has been achieved. An isolation region is provided overlying a semiconductor substrate. Polysilicon traces are provided. A liner oxide layer is formed overlying the polysilicon traces and the insulator layer. A silicon nitride layer is formed overlying the liner oxide layer. A polysilicon or amorphous silicon layer is deposited overlying the silicon nitride layer. The polysilicon or amorphous silicon layer is completely oxidized to form a temporary silicon dioxide layer. The temporary silicon dioxide layer is rounded in the corners due to volume expansion during the oxidation step. The temporary silicon dioxide layer is anisotropically etched through to expose horizontal surfaces of the silicon nitride layer while leaving vertical sidewalls of the temporary silicon dioxide layer. The silicon nitride layer is anisotropically etched to form silicon nitride sidewall spacers with an L-shaped profile. The integrated circuit device is completed.

摘要翻译： 已经实现了形成氮化硅侧壁间隔物的新方法。 此外，已经实现了用于氮化硅侧壁间隔物的新的器件配置。 设置在半导体衬底上的隔离区域。 提供多晶硅痕迹。 在多晶硅迹线和绝缘体层上形成衬里氧化物层。 形成覆盖衬垫氧化物层的氮化硅层。 沉积氮化硅层上的多晶硅或非晶硅层。 多晶硅或非晶硅层被完全氧化以形成临时二氧化硅层。 在氧化步骤期间由于体积膨胀，临时二氧化硅层在角部被倒圆。 临时二氧化硅层被各向异性地蚀刻以暴露氮化硅层的水平表面，同时留下临时二氧化硅层的垂直侧壁。 氮化硅层被各向异性蚀刻以形成具有L形轮廓的氮化硅侧壁间隔物。 集成电路装置完成。

公开(公告)号：US06380087B1

公开(公告)日：2002-04-30

申请号：US09596901

申请日：2000-06-19

申请人： Subhash Gupta ,  Mei Sheng Zhou ,  Ramasamy Chockalingam

发明人： Subhash Gupta ,  Mei Sheng Zhou ,  Ramasamy Chockalingam

IPC分类号： H01L21302

CPC分类号： H01L24/02 ,  H01L21/7684 ,  H01L21/76877 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  Y10S438/926

摘要： A method of fabricating a semiconductor wafer having at least one integrated circuit, the method comprising the following steps. A semiconductor wafer structure having at least an upper and a lower dielectric layer is provided. The semiconductor wafer structure having a bonding pad area and an interconnect area. At least one active interconnect having a first width is formed in the interconnect area, through the dielectric layers. A plurality of adjacent dummy plugs each having a second width is formed in the bonding pad area, through a portion of the dielectric layers. The semiconductor wafer structure is patterned and etched to form trenches through the upper dielectric layer. The trenches surround each of the at least one active interconnect and the dummy plugs whereby the upper dielectric level between the adjacent dummy plugs is removed. A metallization layer is deposited over the lower dielectric layer, filling the trenches at least to the upper surface of the remaining upper dielectric layer. The metallization layer is planarized to remove the excess of the metallization layer forming a continuous bonding pad within the bonding pad area and including the plurality of adjacent dummy plugs, thus forming at least one damascene structure including the at least one respective active interconnect.

摘要翻译： 一种制造具有至少一个集成电路的半导体晶片的方法，所述方法包括以下步骤。 提供了至少具有上介电层和下电介质层的半导体晶片结构。 该半导体晶片结构具有焊盘区域和互连区域。 具有第一宽度的至少一个有源互连通过电介质层形成在互连区域中。 通过电介质层的一部分，在焊盘区域中形成多个具有第二宽度的相邻虚拟插头。 对半导体晶片结构进行图案化和蚀刻，以形成通过上部电介质层的沟槽。 沟槽围绕至少一个有源互连和虚拟插头中的每一个，由此相邻虚拟插头之间的上部电介质层被去除。 金属化层沉积在下电介质层上，至少填充到剩余的上电介质层的上表面上的沟槽。 金属化层被平坦化以去除在焊盘区域内形成连续接合焊盘的多余的金属化层，并且包括多个相邻的虚设插头，从而形成包括至少一个相应的有源互连的至少一个镶嵌结构。

公开(公告)号：US06309982B1

公开(公告)日：2001-10-30

申请号：US09803188

申请日：2001-03-12

申请人： Simon Chooi ,  Yi Xu ,  Yakub Aliyu ,  Mei-Sheng Zhou ,  John Leonard Sudijono ,  Subhash Gupta ,  Sudipto Ranendra Roy ,  Paul Ho

发明人： Simon Chooi ,  Yi Xu ,  Yakub Aliyu ,  Mei-Sheng Zhou ,  John Leonard Sudijono ,  Subhash Gupta ,  Sudipto Ranendra Roy ,  Paul Ho

IPC分类号： H01L2131

CPC分类号： H01L21/02129 ,  H01L21/02126 ,  H01L21/02274 ,  H01L21/3115 ,  H01L21/31612 ,  H01L21/31625

摘要： A method for reducing copper diffusion into an inorganic dielectric layer adjacent to a copper structure by doping the inorganic dielectric layer with a reducing agent (e.g. phosphorous, sulfur, or both) during plasma enhanced chemical vapor deposition. The resulting doped inorganic dielectric layer can reduce copper diffusion without a barrier layer reducing fabrication cost and cycle time, as well as reducing RC delay.

摘要翻译： 一种通过在等离子体增强化学气相沉积期间通过用还原剂（例如磷，硫或两者）掺杂无机介电层来减少铜扩散到与铜结构相邻的无机电介质层中的方法。 所得到的掺杂无机介电层可以减少铜扩散而无需阻挡层降低制造成本和循环时间，并减少RC延迟。

公开(公告)号：US06261955B1

公开(公告)日：2001-07-17

申请号：US09618262

申请日：2000-07-18

申请人： Yakub Aliyu ,  Simon Chooi ,  Mei Sheng Zhou ,  John Leonard Sudijono ,  Subhash Gupta ,  Sudipto Ranendra Roy ,  Paul Kwok Keung Ho ,  Yi Xu

发明人： Yakub Aliyu ,  Simon Chooi ,  Mei Sheng Zhou ,  John Leonard Sudijono ,  Subhash Gupta ,  Sudipto Ranendra Roy ,  Paul Kwok Keung Ho ,  Yi Xu

IPC分类号： H01L2144

CPC分类号： H01L21/02046 ,  C23F1/12 ,  H01L21/02079 ,  Y10S438/906

摘要： An effective copper decontamination method in the fabrication of integrated circuits is achieved. An organic-based HFACAC decontamination compound in vapor phase is sprayed over elemental copper found on equipment or tools or as a spill wherein the compound reacts with all of the elemental copper and forms a volatile compound that can be flushed away thereby completing copper decontamination.

摘要翻译： 实现了集成电路制造中有效的铜去污方法。 蒸气相中的基于有机的HFACAC去污化合物喷洒在设备或工具上发现的元素铜上，或作为溢出物喷洒，其中化合物与所有元素铜反应并形成可被冲洗掉的挥发性化合物，从而完成铜去污。

公开(公告)号：US06225221B1

公开(公告)日：2001-05-01

申请号：US09501966

申请日：2000-02-10

申请人： Paul Kwok Keung Ho ,  Mei Sheng Zhou ,  Subhash Gupta ,  Chockalingam Ramasamy

发明人： Paul Kwok Keung Ho ,  Mei Sheng Zhou ,  Subhash Gupta ,  Chockalingam Ramasamy

IPC分类号： H01L2144

CPC分类号： H01L21/76843 ,  H01L21/76874 ,  H01L21/76876 ,  H01L2221/1089

摘要： A new method of depositing a copper seed layer in the manufacture of an integrated circuit device has been achieved. The copper seed layer is thin and conformal and well-suited for subsequent electroless plating of copper. A dielectric layer, which may comprise a stack of dielectric material, is provided overlying a semiconductor substrate. The dielectric layer patterned to form vias and trenches for planned dual damascene interconnects. A barrier layer comprising tantalum, titanium, or tungsten is deposited overlying the dielectric layer to line the vias and trenches. A copper seed layer is deposited overlying the barrier layer by the reaction of CuF2 vapor with the barrier layer, and the integrated circuit is completed.

摘要翻译： 已经实现了在制造集成电路器件中沉积铜种子层的新方法。 铜种子层薄且保形，非常适合随后的铜化学镀。 提供覆盖在半导体衬底上的介电层，其可以包括电介质材料的叠层。 图案化的电介质层形成用于计划的双镶嵌互连的通孔和沟槽。 包含钽，钛或钨的阻挡层沉积在电介质层上，以对通孔和沟槽进行排列。 通过CuF2蒸汽与阻挡层的反应沉积覆盖阻挡层的铜籽晶层，并且集成电路完成。

公开(公告)号：US06132521A

公开(公告)日：2000-10-17

申请号：US467132

申请日：1999-12-20

申请人： Subhash Gupta ,  Simon Chooi ,  Mei Sheng Zhou ,  Paul Ho

发明人： Subhash Gupta ,  Simon Chooi ,  Mei Sheng Zhou ,  Paul Ho

IPC分类号： C11D3/20 ,  C11D3/39 ,  C23G5/032 ,  B08B3/04

CPC分类号： C11D3/2072 ,  C11D3/2003 ,  C11D3/2093 ,  C11D3/3945 ,  C23G5/032 ,  Y10S134/902

摘要： A method of cleaning elemental copper, cobalt, or nickel from the surface of equipment hardware without corroding or damaging the equipment parts and surfaces in the event of wafer breakage and non-wafer breakage is described. A solution includes an alkyldione peroxide, a stabilizing agent, and alcohols is used to oxidize the metal and form soluble complexes which are removed by the cleaning solution. Also, a alkyldione peroxide solution for cleaning elemental copper, cobalt, or nickel from the surface of equipment hardware in the event of wafer breakage and non-wafer breakage is provided.

摘要翻译： 描述了从设备硬件表面清除元素铜，钴或镍的方法，而不会在晶片断裂和非晶片断裂的情况下腐蚀或损坏设备部件和表面。 溶液包括烷基二酮过氧化物，稳定剂，醇用于氧化金属并形成由清洗溶液除去的可溶性络合物。 此外，提供了在晶片断裂和非晶片断裂的情况下从设备硬件的表面清除元素铜，钴或镍的烷基二氧化碳过氧化物溶液。

公开(公告)号：US6071824A

公开(公告)日：2000-06-06

申请号：US937634

申请日：1997-09-25

申请人： Bhanwar Singh ,  Subhash Gupta ,  Mutya Vicente ,  Susan Hsuching Chen

发明人： Bhanwar Singh ,  Subhash Gupta ,  Mutya Vicente ,  Susan Hsuching Chen

IPC分类号： G03F7/09 ,  H01L21/027 ,  H01L21/3213 ,  H01L21/00

CPC分类号： H01L21/32139 ,  G03F7/091 ,  H01L21/0276

摘要： A method and system for patterning a metal layer of a semiconductor device is disclosed. The method and system includes providing a material with an antireflective low dielectric constant hard mask layer (antireflective low k hard mask layer) on top of the metal layer, and providing a photoresist pattern on top of the anti-reflective low k hard mask layer. The method and system further includes etching of the anti-reflective low k hard mask layer and etching of the metal layer, wherein the photoresist is removed but the anti-reflective low k hard mask layer remains. In a preferred embodiment, the mask layer can also be applied at low temperatures (i.e., >300.degree.) to ensure that the physical properties of the integrated circuit are not affected. Finally, the low k material does not have to be removed after processing. Accordingly, through the use of an anti-reflective low k hard mask layer, the metal patterning can be more effectively accomplished in a deep submicron process, particularly a process that is required for 0.18 microns or smaller technologies.

摘要翻译： 公开了用于图案化半导体器件的金属层的方法和系统。 该方法和系统包括在金属层的顶部提供具有抗反射低介电常数硬掩模层（抗反射低k硬掩模层）的材料，并且在抗反射低k硬掩模层的顶部提供光致抗蚀剂图案。 所述方法和系统还包括蚀刻抗反射低k硬掩模层和蚀刻金属层，其中去除光致抗蚀剂，但保留抗反射低k硬掩模层。 在优选实施例中，掩模层也可以在低温（即> 300°）下施加，以确保集成电路的物理性质不受影响。 最后，低k材料在加工后不必去除。 因此，通过使用抗反射低k硬掩模层，可以在深亚微米工艺中更有效地实现金属图案化，特别是0.18微米或更小技术所需的工艺。

公开(公告)号：US5841196A

公开(公告)日：1998-11-24

申请号：US970314

申请日：1997-11-14

申请人： Subhash Gupta ,  Robert Flores ,  Michael Ross Stamm ,  Eric Thomas Sharp ,  Erich W. E. Denninger ,  Pamela G. Dye ,  Joel Samuel Utz ,  James K. Kai

发明人： Subhash Gupta ,  Robert Flores ,  Michael Ross Stamm ,  Eric Thomas Sharp ,  Erich W. E. Denninger ,  Pamela G. Dye ,  Joel Samuel Utz ,  James K. Kai

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L21/00

CPC分类号： H01L21/76804 ,  H01L23/5226 ,  H01L2924/0002

摘要： A method of forming a via in a interlevel dielectric of a semiconductor device wherein the via has a fluted sidewall. A semiconductor substrate is provided having a first conductive layer formed thereon. A dielectric layer is then formed on the first conductive layer. A photoresist layer is deposited on a dielectric layer and a contact opening is formed in the photoresist layer to expose a contact region of the dielectric layer. A first etch step is performed to remove portions of the dielectric layer proximal to the contact region to form a first stage of the fluted via. The first stage includes a first sidewall stage extending from an upper surface of the dielectric layer at an angle less than 50.degree.. The first stage of the fluted via exterds a first lateral distance which is greater than a lateral dimension of the contact opening. A second etch step is then performed to further remove portions of the dielectric layer to form a second stage of the fluted via. The second stage includes a second sidewall stage extending from the first sidewall stage at a second angle between 40.degree. and 70.degree.. A third etch step is then performed to further remove portions of the dielectric layer to form a third and final. stage of the fluted via. The fluted via extends from an upper surface of the dielectric layer to an upper surface of the first conductive layer. The third stage includes a third stage sidewall extending from said second stage side wall to said upper surface of said first conductive layer at an angle between 60.degree. and 80.degree..

摘要翻译： 一种在半导体器件的层间电介质中形成通孔的方法，其中通孔具有带槽纹的侧壁。 提供具有形成在其上的第一导电层的半导体衬底。 然后在第一导电层上形成电介质层。 在介电层上沉积光致抗蚀剂层，并且在光致抗蚀剂层中形成接触开口以暴露电介质层的接触区域。 执行第一蚀刻步骤以去除接近接触区域的电介质层的部分，以形成槽纹通孔的第一级。 第一级包括从电介质层的上表面以小于50°的角度延伸的第一侧壁级。 槽纹通过的第一阶段通过大于接触开口的横向尺寸的第一横向距离。 然后执行第二蚀刻步骤以进一步去除介电层的部分以形成槽纹通孔的第二级。 第二阶段包括从第一侧壁台以40°至70°之间的第二角度延伸的第二侧壁台。 然后执行第三蚀刻步骤以进一步去除介电层的部分以形成第三和最终。 槽的通道的阶段。 带槽通孔从电介质层的上表面延伸到第一导电层的上表面。 第三级包括第三级侧壁，从第二级侧壁延伸至所述第一导电层的上表面，角度为60°至80°。

公开(公告)号：US5814560A

公开(公告)日：1998-09-29

申请号：US564752

申请日：1995-11-29

申请人： Robin W. Cheung ,  Simon S. Chan ,  Subhash Gupta

发明人： Robin W. Cheung ,  Simon S. Chan ,  Subhash Gupta

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L21/4763

CPC分类号： H01L21/76886 ,  H01L23/5283 ,  H01L23/53223 ,  H01L2924/0002

摘要： A method is provided for forming metal interconnect structures which resists the formation of pile-ups caused by electromigration. Each metal interconnect structure includes an aluminum interconnect sandwiched between two refractory metal layers. The method of the present invention involves forming a layer of aluminum intermetallic alloy on the sidewalls of the aluminum interconnects. The layer of aluminum intermetallic alloy provides reinforcement for the sidewalls. The layer of aluminum intermetallic alloy comprises aluminum-refractory metal alloy. The aluminum-refractory metal alloy is formed by reacting the exposed aluminum on the sidewalls with refractory metal-containing precursor material. After the formation of the layer of aluminum intermetallic alloy the sidewalls of the aluminum interconnects, the formation of pile-ups will be suppressed. Thus, the lifetime of the aluminum interconnects is extended. Accordingly, the method of the present invention improves the reliability and wear resistance of integrated circuits employing aluminum interconnects.

摘要翻译： 提供一种用于形成金属互连结构的方法，其抵抗由电迁移引起的堆积的形成。 每个金属互连结构包括夹在两个难熔金属层之间的铝互连。 本发明的方法包括在铝互连件的侧壁上形成铝金属间合金层。 铝金属间合金层为侧壁提供加固。 铝金属间合金层包括铝 - 难熔金属合金。 铝 - 难熔金属合金是通过将侧壁上暴露的铝与含难熔金属的前体材料反应而形成的。 在形成铝金属间合金层之后，铝互连的侧壁，堆积的形成将被抑制。 因此，铝互连的寿命延长。 因此，本发明的方法提高了采用铝互连的集成电路的可靠性和耐磨性。

公开(公告)号：US5717621A

公开(公告)日：1998-02-10

申请号：US411918

申请日：1995-03-28

申请人： Subhash Gupta ,  Ravi Mehrotra

发明人： Subhash Gupta ,  Ravi Mehrotra

IPC分类号： G06F17/12 ,  G06F7/38

CPC分类号： G06F17/12

摘要： An apparatus and method for solving a system of linear equations uses a sequence of matrix-vector multiplications wherein the matrix to be multiplied is derived from an expansion point matrix that permits rapid convergence. The matrix-vector multiplication form of the sequence permits calculations to be performed on a network of parallel processors.

摘要翻译： 用于求解线性方程组的装置和方法使用矩阵向量乘法序列，其中要乘以的矩阵从允许快速收敛的扩展点矩阵导出。 序列的矩阵向量乘法形式允许在并行处理器的网络上执行计算。