公开(公告)号：US20050167786A1

公开(公告)日：2005-08-04

申请号：US10708023

申请日：2004-02-03

申请人： Jason Gill ,  Terence Hook ,  Randy Mann ,  William Murphy ,  William Tonti ,  Steven Voldman

发明人： Jason Gill ,  Terence Hook ,  Randy Mann ,  William Murphy ,  William Tonti ,  Steven Voldman

IPC分类号： H01L21/8244 ,  H01L27/02 ,  H01L27/08 ,  H01L27/11 ,  H01L27/12 ,  H01L27/082

CPC分类号： H01L27/11 ,  H01L27/0288 ,  H01L27/0802 ,  H01L27/1112 ,  H01L27/1203 ,  H01L29/7304 ,  H01L29/7378 ,  H01L29/7391 ,  H01L29/78 ,  Y10S257/903 ,  Y10S257/904

摘要： A method and system for forming a semiconductor device having superior ESD protection characteristics. A resistive material layer is disposed within a contact hole on at least one of the contact stud upper and lower surface. In preferred embodiments, the integral resistor has a resistance value of between about one Ohm and about ten Ohms, or between 10 and 100 Ohms. Embodiments of the resistive layer include sputtered silicon material, a tunnel oxide, a tunnel nitride, a silicon-implanted oxide, a silicon-implanted nitride, or an amorphous polysilicon. Embodiments of the invention include SRAMs, bipolar transistors, SOI lateral diodes, MOSFETs and SiGe Transistors.

摘要翻译： 一种用于形成具有优异的ESD保护特性的半导体器件的方法和系统。 电阻材料层设置在触头螺柱上下表面中的至少一个上的接触孔内。 在优选实施例中，积分电阻器的电阻值介于约1欧姆至约10欧姆之间，或10欧姆至100欧姆之间。 电阻层的实施例包括溅射硅材料，隧道氧化物，隧道氮化物，硅注入氧化物，注入硅的氮化物或非晶多晶硅。 本发明的实施例包括SRAM，双极晶体管，SOI横向二极管，MOSFET和SiGe晶体管。

公开(公告)号：US06882027B2

公开(公告)日：2005-04-19

申请号：US10447018

申请日：2003-05-28

申请人： Axel Brintzinger ,  Carl Radens ,  William Tonti

发明人： Axel Brintzinger ,  Carl Radens ,  William Tonti

IPC分类号： H01L23/525 ,  H01L29/00

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods and apparatus for providing an antifuse are disclosed, where the antifuse includes a semiconductor substrate having an active area circumscribed by a shallow trench isolation (STI) boundary; a gate conductor disposed above the semiconductor substrate and overlying at least a portion of the STI boundary; a dielectric disposed between the semiconductor substrate and the gate conductor; a first terminal coupled to the gate conductor; and a second terminal coupled to the semiconductor substrate, wherein a breakdown of the dielectric causes electrical connections between regions of the gate conductor and regions of the active area including substantially near the STI boundary.

摘要翻译： 公开了用于提供反熔丝的方法和装置，其中反熔丝包括具有由浅沟槽隔离（STI）边界限定的有源区的半导体衬底; 栅极导体，其设置在所述半导体衬底上方并且覆盖所述STI边界的至少一部分; 设置在所述半导体衬底和所述栅极导体之间​​的电介质; 耦合到所述栅极导体的第一端子; 以及耦合到所述半导体衬底的第二端子，其中所述电介质的击穿导致所述栅极导体的区域和所述有源区域的区域之间的电连接包括基本上靠近所述STI边界。

公开(公告)号：US20050073354A1

公开(公告)日：2005-04-07

申请号：US10605466

申请日：2003-10-01

申请人： Wagdi Abadeer ,  John Fifield ,  William Tonti

发明人： Wagdi Abadeer ,  John Fifield ,  William Tonti

IPC分类号： G11C5/14 ,  H01L27/08 ,  H01L27/088 ,  H02J1/00 ,  H02M3/00

CPC分类号： G11C5/147 ,  H01L27/0802 ,  H01L27/088 ,  H02M3/00

摘要： A voltage divider for integrated circuits that does not include the use of resistors. In one embodiment, voltage node VDD is connected with two n-type transistors, NFET1 and NFET2, which are connected in series. NFET 1 includes a source (12), a drain (14), a gate electrode (16) having a gate area A1 (not shown), and a p-substrate (18). NFET2 includes a source (20), a drain (22), a gate electrode (24) having a gate area A2 (not shown), and a p-substrate (26). Source (12) and drain (14) of NFET1 are coupled with gate electrode (24) of NFET2. The voltage difference between NFET1 and NFET2 has a linear function with VDD. As a result, voltage VDD may be divided between NFET1 and NFET2 by properly choosing the ratio between each of the respective transistor gate electrode areas, (A1) and (A2).

摘要翻译： 用于集成电路的分压器，不包括使用电阻器。 在一个实施例中，电压节点VDD与串联连接的两个n型晶体管NFET1和NFET2连接。 NFET 1包括源极（12），漏极（14），具有栅极区域A1（未示出）的栅电极（16）和p衬底（18）。 NFET2包括源极（20），漏极（22），具有栅极区域A2（未示出）的栅电极（24）和p衬底（26）。 NFET1的源极（12）和漏极（14）与NFET2的栅电极（24）耦合。 NFET1和NFET2之间的电压差与VDD具有线性关系。 结果，通过适当地选择各个晶体管栅电极区域（A1）和（A2）之间的比率，可以在NFET1和NFET2之间划分电压VDD。

公开(公告)号：US20130001789A1

公开(公告)日：2013-01-03

申请号：US13617060

申请日：2012-09-14

申请人： Chih-Chao Yang ,  Veeraraghavan S. Basker ,  William Tonti ,  Keith K. H. Wong

发明人： Chih-Chao Yang ,  Veeraraghavan S. Basker ,  William Tonti ,  Keith K. H. Wong

IPC分类号： H01L23/48

CPC分类号： H01L21/76843 ,  H01L21/76814 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76886 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Interconnect structures having improved electromigration resistance are provided that include a metallic interfacial layer (or metal alloy layer) that is present at the bottom of a via opening. The via opening is located within a second dielectric material that is located atop a first dielectric material that includes a first conductive material embedded therein. The metallic interfacial layer (or metal alloy layer) that is present at the bottom of the via opening is located between the underlying first conductive material embedded within the first dielectric and the second conductive material that is embedded within the second dielectric material. Methods of fabricating the improved electromigration resistance interconnect structures are also provided.

摘要翻译： 提供具有改善的电迁移阻力的互连结构，其包括存在于通孔开口底部的金属界面层（或金属合金层）。 通孔开口位于第二电介质材料内，第二电介质材料位于包括嵌入其中的第一导电材料的第一电介质材料的顶部。 存在于通孔开口底部的金属界面层（或金属合金层）位于埋在第一电介质内的下面的第一导电材料和嵌入在第二电介质材料内的第二导电材料之间。 还提供了制造改进的电迁移电阻互连结构的方法。

公开(公告)号：US08288276B2

公开(公告)日：2012-10-16

申请号：US12346040

申请日：2008-12-30

申请人： Chih-Chao Yang ,  Veeraraghavan S. Basker ,  William Tonti ,  Keith Kwong Hon Wong

发明人： Chih-Chao Yang ,  Veeraraghavan S. Basker ,  William Tonti ,  Keith Kwong Hon Wong

IPC分类号： H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/76814 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76886 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Interconnect structures having improved electromigration resistance are provided that include a metallic interfacial layer (or metal alloy layer) that is present at the bottom of a via opening. The via opening is located within a second dielectric material that is located atop a first dielectric material that includes a first conductive material embedded therein. The metallic interfacial layer (or metal alloy layer) that is present at the bottom of the via opening is located between the underlying first conductive material embedded within the first dielectric and the second conductive material that is embedded within the second dielectric material. Methods of fabricating the improved electromigration resistance interconnect structures are also provided.

摘要翻译： 提供具有改善的电迁移阻力的互连结构，其包括存在于通孔开口底部的金属界面层（或金属合金层）。 通孔开口位于第二电介质材料内，第二电介质材料位于包括嵌入其中的第一导电材料的第一电介质材料的顶部。 存在于通孔开口底部的金属界面层（或金属合金层）位于埋在第一电介质内的下面的第一导电材料和嵌入在第二电介质材料内的第二导电材料之间。 还提供了制造改进的电迁移电阻互连结构的方法。

公开(公告)号：US08232177B2

公开(公告)日：2012-07-31

申请号：US12570415

申请日：2009-09-30

申请人： Wagdi Abadeer ,  Lilian Kamal, legal representative ,  Kiran V Chatty ,  Robert J Gauthier, Jr. ,  Jed H Rankin ,  Robert R Robison ,  William Tonti

发明人： Wagdi Abadeer ,  Kiran V Chatty ,  Robert J Gauthier, Jr. ,  Jed H Rankin ,  Robert R Robison ,  William Tonti

IPC分类号： H01L21/76

CPC分类号： H01L21/76232

摘要： A solution for alleviating variable parasitic bipolar leakages in scaled semiconductor technologies is described herein. Placement variation is eliminated for edges of implants under shallow trench isolation (STI) areas by creating a barrier to shield areas from implantation more precisely than with only a standard photolithographic mask. An annealing process expands the implanted regions such their boundaries align within a predetermined distance from the edge of a trench. The distances are proportionate for each trench and each adjacent isolation region.

摘要翻译： 本文描述了用于减小缩放半导体技术中的可变寄生双极性泄漏的解决方案。 在浅沟槽隔离（STI）区域下的植入物的边缘，通过与仅使用标准光刻掩模相比更加精确地产生屏蔽区域而不是植入屏蔽区域来消除放置变化。 退火处理使注入区域扩展，使其边界在与沟槽边缘预定距离内对齐。 距离对于每个沟槽和每个相邻的隔离区域是成比例的。

公开(公告)号：US08101505B2

公开(公告)日：2012-01-24

申请号：US12135242

申请日：2008-06-09

申请人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam ,  William Tonti

发明人： Michel J. Abou-Khalil ,  Robert J. Gauthier, Jr. ,  Tom C. Lee ,  Junjun Li ,  Souvick Mitra ,  Christopher S. Putnam ,  William Tonti

IPC分类号： H01L21/479 ,  H01L23/52

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to e-fuse devices, and more particularly to a device and method of forming an e-fuse device, the method comprising providing a first conductive layer connected to a second conductive layer, the first and second conductive layers separated by a barrier layer having a first diffusivity different than a second diffusivity of the first conductive layer. A void is created in the first conductive layer by driving an electrical current through the e-fuse device.

摘要翻译： 本发明涉及电熔丝装置，更具体地说，涉及一种形成电熔丝装置的装置和方法，所述方法包括提供连接到第二导电层的第一导电层，所述第一和第二导电层由 阻挡层具有与第一导电层的第二扩散率不同的第一扩散率。 通过驱动电流通过电熔丝装置而在第一导电层中产生空隙。

公开(公告)号：US20110073985A1

公开(公告)日：2011-03-31

申请号：US12570415

申请日：2009-09-30

申请人： Wagdi W. Abadeer ,  Lilian Kamal ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Robert R. Robison ,  William Tonti

发明人： Wagdi W. Abadeer ,  Lilian Kamal ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Robert R. Robison ,  William Tonti

IPC分类号： H01L29/06 ,  H01L23/00 ,  H01L21/762

CPC分类号： H01L21/76232

摘要： A solution for alleviating variable parasitic bipolar leakages in scaled semiconductor technologies is described herein. Placement variation is eliminated for edges of implants under shallow trench isolation (STI) areas by creating a barrier to shield areas from implantation more precisely than with only a standard photolithographic mask. An annealing process expands the implanted regions such their boundaries align within a predetermined distance from the edge of a trench. The distances are proportionate for each trench and each adjacent isolation region.

摘要翻译： 本文描述了用于减小缩放半导体技术中的可变寄生双极性泄漏的解决方案。 在浅沟槽隔离（STI）区域下的植入物的边缘，通过与仅使用标准光刻掩模相比更加精确地产生屏蔽区域而不是植入屏蔽区域来消除放置变化。 退火处理使注入区域扩展，使其边界在与沟槽边缘预定距离内对齐。 距离对于每个沟槽和每个相邻的隔离区域是成比例的。

公开(公告)号：US07768130B2

公开(公告)日：2010-08-03

申请号：US11939671

申请日：2007-11-14

申请人： Louis Lu-Chen Hsu ,  Jack Allan Mandelman ,  William Tonti ,  Chih-Chao Yang

发明人： Louis Lu-Chen Hsu ,  Jack Allan Mandelman ,  William Tonti ,  Chih-Chao Yang

IPC分类号： H01L23/52

CPC分类号： H01L23/5329 ,  H01L21/7682 ,  H01L21/76849 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/942 ,  H01L2924/00

摘要： A method for fabricating and back-end-of-line (BEOL) metalization structures includes simultaneous high-k and low-k dielectric regions. An interconnect structure includes a first inter-level dielectric (ILD) layer and a second ILD layer with the first ILD layer underlying the second ILD layer. A plurality of columnar air gaps is formed in the first ILD. The columnar air gap structure is created using a two-phase photoresist material for providing different etching selectivity during subsequent processing.

摘要翻译： 一种用于制造和后端（BEOL）金属化结构的方法包括同时存在的高k和低k电介质区域。 互连结构包括第一层间电介质（ILD）层和具有位于第二ILD层下面的第一ILD层的第二ILD层。 在第一ILD中形成多个柱状气隙。 使用两相光致抗蚀剂材料制造柱状气隙结构，用于在随后的处理期间提供不同的蚀刻选择性。

公开(公告)号：US20100164111A1

公开(公告)日：2010-07-01

申请号：US12346040

申请日：2008-12-30

申请人： Chih-Chao Yang ,  Veeraraghavan S. Basker ,  William Tonti ,  Keith Kwong Hon Wong

发明人： Chih-Chao Yang ,  Veeraraghavan S. Basker ,  William Tonti ,  Keith Kwong Hon Wong

IPC分类号： H01L23/52 ,  H01L21/768

CPC分类号： H01L21/76843 ,  H01L21/76814 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76886 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Interconnect structures having improved electromigration resistance are provided that include a metallic interfacial layer (or metal alloy layer) that is present at the bottom of a via opening. The via opening is located within a second dielectric material that is located atop a first dielectric material that includes a first conductive material embedded therein. The metallic interfacial layer (or metal alloy layer) that is present at the bottom of the via opening is located between the underlying first conductive material embedded within the first dielectric and the second conductive material that is embedded within the second dielectric material. Methods of fabricating the improved electromigration resistance interconnect structures are also provided.

摘要翻译： 提供具有改善的电迁移阻力的互连结构，其包括存在于通孔开口底部的金属界面层（或金属合金层）。 通孔开口位于第二电介质材料内，第二电介质材料位于包括嵌入其中的第一导电材料的第一电介质材料的顶部。 存在于通孔开口底部的金属界面层（或金属合金层）位于埋在第一电介质内的下面的第一导电材料和嵌入在第二电介质材料内的第二导电材料之间。 还提供了制造改进的电迁移电阻互连结构的方法。