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    Coordinated near-far memory controller for process-in-HBM
    93.
    发明授权
    Coordinated near-far memory controller for process-in-HBM 有权

    公开(公告)号：US10437482B2

    公开(公告)日：2019-10-08

    申请号：US15723014

    申请日：2017-10-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mu-Tien Chang ,  Dimin Niu ,  Hongzhong Zheng

    IPC: G06F3/06 ,  G06F12/02

    Abstract: A method of coordinating memory commands in a high-bandwidth memory HBM+ system, the method including sending a host memory controller command from a host memory controller to a memory, receiving the host memory controller command at a coordinating memory controller, forwarding the host memory controller command from the coordinating memory controller to the memory, and scheduling, by the coordinating memory controller, a coordinating memory controller command based on the host memory controller command.

    DRAM ASSIST ERROR CORRECTION MECHANISM FOR DDR SDRAM INTERFACE
    94.
    发明申请
    DRAM ASSIST ERROR CORRECTION MECHANISM FOR DDR SDRAM INTERFACE 审中-公开

    公开(公告)号：US20190179705A1

    公开(公告)日：2019-06-13

    申请号：US16276369

    申请日：2019-02-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dimin Niu ,  Mu-Tien Chang ,  Hongzhong Zheng ,  Hyun-Joong Kim ,  Won-hyung Song ,  Jangseok Choi

    IPC: G06F11/10 ,  G11C29/42 ,  G11C29/52 ,  G11C5/04

    Abstract: A method of correcting a memory error of a dynamic random-access memory module (DRAM) using a double data rate (DDR) interface, the method includes conducting a memory transaction including multiple bursts with a memory controller to send data from data chips of the DRAM to the memory controller, detecting one or more errors using an ECC chip of the DRAM, determining a number of the bursts having the errors using the ECC chip of the DRAM, determining whether the number of the bursts having the errors is greater than a threshold number, determining a type of the errors, and directing the memory controller based on the determined type of the errors, wherein the DRAM includes a single ECC chip per memory channel.

    TECHNIQUES TO REDUCE READ-MODIFY-WRITE OVERHEAD IN HYBRID DRAM/NAND MEMORY
    97.
    发明申请
    TECHNIQUES TO REDUCE READ-MODIFY-WRITE OVERHEAD IN HYBRID DRAM/NAND MEMORY 审中-公开

    公开(公告)号：US20180293175A1

    公开(公告)日：2018-10-11

    申请号：US15662072

    申请日：2017-07-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mu-Tien Chang ,  Heehyun Nam ,  Youngsik Kim ,  Youngjin Cho ,  Dimin Niu ,  Hongzhong Zheng

    IPC: G06F12/121

    Abstract: A method of choosing a cache line of a plurality of cache lines of data for eviction from a frontend memory, the method including assigning a baseline replacement score to each way of a plurality of ways of a cache, the ways respectively storing the cache lines, assigning a validity score to each way based on a degree of validity of the cache line stored in each way, assigning an eviction decision score to each way based on a function of the baseline replacement score for the way and the validity score for the way, and choosing a cache line of the way having a highest eviction decision score as the cache line for eviction.

    Smart in-module refresh for DRAM
    99.
    发明授权
    Smart in-module refresh for DRAM 有权

    公开(公告)号：US09761296B2

    公开(公告)日：2017-09-12

    申请号：US15299445

    申请日：2016-10-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mu-Tien Chang ,  Krishna Malladi ,  Dimin Niu ,  Hongzhong Zheng

    IPC: G11C5/14 ,  G11C11/406 ,  G11C11/4076 ,  G11C5/04 ,  G06F13/16

    CPC classification number: G11C11/40615 ,  G06F13/1636 ,  G11C5/04 ,  G11C11/40618 ,  G11C11/4076

    Abstract: A memory (1205) is disclosed. The memory (1205) can includes a stack of dynamic Random Access Memory (DRAM) cores (1210, 1215, 1220, 1225) in a three-dimensional stacked memory architecture (1230). Each of the DRAM cores (1210, 1215, 1220, 1225) can include a plurality of banks (205-1, 205-2, 205-3, 205-4) to store data. The memory (1205) can also include logic layer (1235) which can include an interface (1305) to connect the memory (1205) with a processor (120). The logic layer (1235) can also include a refresh engine (115) that can be used to refresh one of the plurality of banks (205-1, 205-2, 205-3, 205-4) and a Smart Refresh Component (305) that can advise the refresh engine (115) which bank to refresh using an out-of-order per-bank refresh. The Smart Refresh Component (305) can use a logic (415) to identify a farthest bank in the pending transactions in the transaction queue (430) at the time of refresh.

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