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    Semiconductor devices
    92.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US11805639B2

    公开(公告)日：2023-10-31

    申请号：US17372634

    申请日：2021-07-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Euna Kim ,  Keunnam Kim ,  Kiseok Lee ,  Wooyoung Choi ,  Sunghee Han

    IPC: H10B12/00 ,  H01L23/528

    CPC classification number: H10B12/315 ,  H01L23/528 ,  H10B12/0335 ,  H10B12/482 ,  H10B12/485

    Abstract: A semiconductor device includes a substrate including an active region, a first bitline structure and a second bitline structure that extend side by side on the substrate, a storage node contact electrically connected to the active region between the first and second bitline structures, a lower landing pad between the first and second bitline structures and on the storage node contact, an upper landing pad in contact with the first bitline structure and electrically connected to the lower landing pad, and a capping insulating layer. A lower surface of the upper landing pad in contact with the first bitline structure and a lower surface of the capping insulating layer in contact with the lower landing pad each include a portion in which a horizontal separation distance is increased from the adjacent upper landing pad in a direction toward the substrate.

    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    93.
    发明公开
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230345696A1

    公开(公告)日：2023-10-26

    申请号：US18132198

    申请日：2023-04-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seokhan Park ,  Bowon Yoo ,  Hyunseo Shin ,  Kiseok Lee ,  Moonyoung Jeong

    IPC: H10B12/00

    CPC classification number: H10B12/0387 ,  H10B12/0383 ,  H10B12/488

    Abstract: A method of manufacturing a semiconductor device includes forming a plurality of first trenches in a substrate. A plurality of first filling layers is formed that fills the first trenches and have protrusions extending to protrude from the substrate. Spacers are formed on sidewalls of the protrusions of the first filling layers. The spacers expose portions of the substrate between adjacent first filling layers. A plurality of second trenches is formed around the first trenches by etching the portions of the substrate exposed by the spacers. A plurality of second filling layers is formed that fills the second trenches. All of the first filling layers and the spacers are removed. A gate material layer is formed that conformally covers inner walls of the first trenches. A pair of gate structures is formed in each of the first trenches by separating the gate material layer.

    Semiconductor memory device and method of fabricating the same
    95.
    发明授权
    Semiconductor memory device and method of fabricating the same 有权

    公开(公告)号：US11600570B2

    公开(公告)日：2023-03-07

    申请号：US17097337

    申请日：2020-11-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyo-Sub Kim ,  Sohyun Park ,  Daewon Kim ,  Dongoh Kim ,  Eun A Kim ,  Chulkwon Park ,  Taejin Park ,  Kiseok Lee ,  Sunghee Han

    IPC: H01L23/535 ,  H01L21/768 ,  H01L27/108 ,  H01L23/532

    Abstract: A semiconductor memory device is disclosed. The device may include first and second impurity regions provided in a substrate and spaced apart from each other, the second impurity region having a top surface higher than the first impurity region, a device isolation pattern interposed between the first and second impurity regions, a first contact plug, which is in contact with the first impurity region and has a bottom surface lower than the top surface of the second impurity region, a gap-fill insulating pattern interposed between the first contact plug and the second impurity region, a first protection spacer interposed between the gap-fill insulating pattern and the second impurity region, and a first spacer, which is in contact with a side surface of the first contact plug and the device isolation pattern and is interposed between the first protection spacer and the gap-fill insulating pattern.

    Three-dimensional semiconductor device with a bit line perpendicular to a substrate
    96.
    发明授权
    Three-dimensional semiconductor device with a bit line perpendicular to a substrate 有权

    公开(公告)号：US11563005B2

    公开(公告)日：2023-01-24

    申请号：US16930398

    申请日：2020-07-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Minsu Lee ,  Kiseok Lee ,  Minwoo Song ,  Hyun-Sil Oh ,  Min Hee Cho

    IPC: H01L27/108 ,  G11C8/14 ,  G11C7/18

    Abstract: A three-dimensional semiconductor device includes a first channel pattern on and spaced apart from a substrate, the first channel pattern having a first end and a second end that are spaced apart from each other in a first direction parallel to a top surface of the substrate, and a first sidewall and a second sidewall connecting between the first end and the second end, the first and second sidewalls being spaced apart from each other in a second direction parallel to the top surface of the substrate, the second direction intersecting the first direction, a bit line in contact with the first end of the first channel pattern, the bit line extending in a third direction perpendicular to the top surface of the substrate, and a first gate electrode adjacent to the first sidewall of the first channel pattern.

    Variable resistance memory device
    97.
    发明授权
    Variable resistance memory device 有权

    公开(公告)号：US11538861B2

    公开(公告)日：2022-12-27

    申请号：US17167851

    申请日：2021-02-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hui-Jung Kim ,  Kiseok Lee ,  Keunnam Kim ,  Yoosang Hwang

    IPC: H01L47/00 ,  H01L27/24 ,  H01L45/00 ,  H01L43/08

    Abstract: Disclosed is a variable resistance memory device including a first conductive line extending in a first direction parallel to a top surface of the substrate, memory cells spaced apart from each other in the first direction on a side of the first conductive line and connected to the first conductive line, and second conductive lines respectively connected to the memory cells. Each second conductive line is spaced apart in a second direction from the first conductive line. The second direction is parallel to the top surface of the substrate and intersects the first direction. The second conductive lines extend in a third direction perpendicular to the top surface of the substrate and are spaced apart from each other in the first direction. Each memory cell includes a variable resistance element and a select element that are positioned at a same level horizontally arranged in the second direction.

    Semiconductor memory devices
    98.
    发明授权
    Semiconductor memory devices 有权

    公开(公告)号：US11355509B2

    公开(公告)日：2022-06-07

    申请号：US17000857

    申请日：2020-08-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kiseok Lee ,  Junsoo Kim ,  Hui-Jung Kim ,  Bong-Soo Kim ,  Satoru Yamada ,  Kyupil Lee ,  Sunghee Han ,  Hyeongsun Hong ,  Yoosang Hwang

    IPC: H01L27/11556 ,  H01L23/532 ,  G11C7/18 ,  H01L49/02 ,  G11C8/14 ,  H01L27/11524 ,  G11C11/404 ,  G11C11/4097

    Abstract: A semiconductor memory device comprises a stack structure including a plurality of layers vertically stacked on a substrate. Each of the plurality of layers includes a first dielectric layer, a semiconductor layer, and a second dielectric layer that are sequentially stacked, and a first conductive line in the second dielectric layer and extending in a first direction. The device also comprises a second conductive line extending vertically through the stack structure, and a capacitor in the stack structure and spaced apart from the second conductive line. The semiconductor layer comprises semiconductor patterns extending in a second direction intersecting the first direction between the first conductive line and the substrate. The second conductive line is between a pair of the semiconductor patterns adjacent to each other in the first direction. An end of each of the semiconductor patterns is electrically connected to a first electrode of the capacitor.

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