公开(公告)号：US08647607B2

公开(公告)日：2014-02-11

申请号：US11414435

申请日：2006-04-28

申请人： Ji-Young Kim ,  Jong-Ho Kim ,  Sug-Youn Chang ,  Sei-Young Yun

发明人： Ji-Young Kim ,  Jong-Ho Kim ,  Sug-Youn Chang ,  Sei-Young Yun

IPC分类号： A61K8/00 ,  A61Q11/00

CPC分类号： A61Q11/00 ,  A61K8/0208 ,  A61K8/22 ,  A61K8/24 ,  A61K8/8164 ,  A61K8/817 ,  A61K8/8176 ,  A61K8/8182

摘要： The present invention relates to a dry type tooth-whitening patch comprising peroxide as a tooth whitening agent. In particular, disclosed is a dry type tooth-whitening patch in which peroxide is contained, as a teeth whitening agent, in a matrix type adhesive layer. The adhesive layer includes, as a base polymer thereof, a hydrophilic glass polymer, which provides a strong adhesion to teeth while releasing the tooth whitening agent when hydrated on the enamel layers of teeth in the moist oral cavity.The dry type patch according to the present invention is convenient in use, as compared to wet type patches. Further, it exhibits a superior adhesion while being maintained in a state attached to the teeth for a lengthened period of time so as to assure an enough contact time between the whitening agent in the patch and stains on the teeth, thereby giving a sufficient whitening effect.

摘要翻译： 本发明涉及含有过氧化物作为牙齿增白剂的干式牙齿美白贴剂。 具体地，公开了在基质型粘合剂层中含有作为牙齿增白剂的过氧化物的干性牙齿增白贴剂。 粘合剂层包括作为其基础聚合物的亲水性玻璃聚合物，其在湿润口腔中的牙齿的牙釉质层上水合时释放牙齿增白剂，同时提供对牙齿的强粘合性。 与湿式贴剂相比，本发明的干型贴剂使用方便。 此外，它表现出优异的粘附性，同时保持在附着于牙齿的状态下延长一段时间，以确保贴剂中的增白剂和牙齿上的污渍之间的足够的接触时间，从而产生足够的美白效果 。

公开(公告)号：US20130004751A1

公开(公告)日：2013-01-03

申请号：US13634485

申请日：2011-03-15

申请人： Cheng-Zhe Huang ,  Ji-Young Kim ,  Ki-Bong Park ,  Chang-Won Kang ,  Jun-Hyuk Kwon ,  Hyun-Jong Kwon ,  Sang-Sun Park ,  Jang-Ki Kim ,  Gyeong-Min Lee

发明人： Cheng-Zhe Huang ,  Ji-Young Kim ,  Ki-Bong Park ,  Chang-Won Kang ,  Jun-Hyuk Kwon ,  Hyun-Jong Kwon ,  Sang-Sun Park ,  Jang-Ki Kim ,  Gyeong-Min Lee

IPC分类号： E04F15/10 ,  B32B27/30 ,  B32B27/08 ,  B32B27/36

CPC分类号： B32B27/36 ,  B32B2307/412 ,  B32B2471/00 ,  E04F15/105 ,  E04F15/107 ,  Y10T428/24868

摘要： Disclosed is a flooring material using an environment-friendly PLA resin. According to the present invention, the flooring material using the PLA resin comprises: a base layer; a print layer which is formed on top of the base layer, and has a print pattern on an upper side thereof; and a transparent layer which is formed on top of the print layer, wherein one or more of the base layer, the print layer, and the transparent layer include polylactic acid (PLA) resin.

摘要翻译： 公开了使用环保型PLA树脂的地板材料。 根据本发明，使用PLA树脂的地板材料包括：基层; 印刷层，其形成在所述基底层的顶部，并且在其上侧具有印刷图案; 以及形成在所述印刷层的顶部的透明层，其中所述基材层，所述印刷层和所述透明层中的一个或多个包括聚乳酸（PLA）树脂。

公开(公告)号：US20130004703A1

公开(公告)日：2013-01-03

申请号：US13634465

申请日：2011-03-30

申请人： Hyun-Jong Kwon ,  Ji-Young Kim ,  Ki-Bong Park ,  Chang-Won Kang ,  Jun-Hyuk Kwon ,  Sang-Sun Park ,  Jang-Ki Kim ,  Gyeong-Min Lee ,  Cheng Zhe Huang

发明人： Hyun-Jong Kwon ,  Ji-Young Kim ,  Ki-Bong Park ,  Chang-Won Kang ,  Jun-Hyuk Kwon ,  Sang-Sun Park ,  Jang-Ki Kim ,  Gyeong-Min Lee ,  Cheng Zhe Huang

IPC分类号： B32B27/36 ,  B32B15/08 ,  B32B27/08 ,  B32B21/02 ,  B32B27/12 ,  B32B5/12 ,  B32B3/26 ,  B32B17/02 ,  B32B3/06 ,  B32B3/10 ,  B32B18/00 ,  B32B7/12

CPC分类号： B32B15/08 ,  B32B9/045 ,  B32B13/12 ,  B32B21/08 ,  B32B27/065 ,  B32B27/12 ,  B32B2262/101 ,  B32B2419/04 ,  B32B2471/00 ,  Y10T428/24066 ,  Y10T428/24612 ,  Y10T428/24802 ,  Y10T428/249982 ,  Y10T428/27 ,  Y10T428/31515 ,  Y10T428/31522 ,  Y10T428/31565 ,  Y10T428/31616 ,  Y10T428/31667 ,  Y10T428/31786 ,  Y10T428/31797 ,  Y10T442/3862

摘要： The present invention relates to a board complex having a polylactic acid (PLA) cover. The board complex includes: a cover member having at least one layer containing a PLA resin; and a board formed beneath the cover member, wherein the material for the board is selected from medium-density fiberboard (MDF), plywood, asbestos-free cellulose fiber reinforced cement board, magnesium board, glued laminated timber, high density fiberboard (HDF), particle board, ceramic tile, porcelain tile, ceramic board, and click-fastened board.

摘要翻译： 本发明涉及具有聚乳酸（PLA）覆盖层的基板复合体。 板复合体包括：具有至少一层含有PLA树脂的层的盖构件; 以及形成在盖构件下方的板，其中用于板的材料选自中密度纤维板（MDF），胶合板，无石棉纤维素纤维增强水泥板，镁板，胶合层压木材，高密度纤维板（HDF） ，刨花板，瓷砖，瓷砖，陶瓷板和点击式紧固板。

公开(公告)号：US07914594B2

公开(公告)日：2011-03-29

申请号：US12180289

申请日：2008-07-25

申请人： Chang-Min Cho ,  Joo-Young Kim ,  Ji-Young Kim ,  Ju-A Ryu ,  Yo-Han Ahn ,  Hyung-Seok Choi ,  Dong-Seok Ham

发明人： Chang-Min Cho ,  Joo-Young Kim ,  Ji-Young Kim ,  Ju-A Ryu ,  Yo-Han Ahn ,  Hyung-Seok Choi ,  Dong-Seok Ham

IPC分类号： B01D46/00

CPC分类号： B01D46/0058 ,  B01D46/002 ,  B01D46/24 ,  B01D46/4272 ,  Y10S55/31

摘要： An air filtering device and an air cleaning system of a semiconductor manufacturing apparatus to reduce cost and increase manufacturing productivity. The air filtering device may include a frame having an open aperture coupled to an air supply line. A buffer frame configured to be inserted into the frame may include a plurality of slot parts, each slot part having a plurality of air in/out apertures through which air may flow in or out from the buffer frame. A plurality of filters may be releasably fastened to the plurality of slot parts to filter pollution material contained in air flowing through the air in/out apertures. An air interrupter for interrupting air flowing through the air in/out apertures may be used when replacing the plurality of filters, thereby providing purified air to the semiconductor manufacturing apparatus during the replacement.

摘要翻译： 一种半导体制造装置的空气过滤装置和空气净化系统，以降低成本并提高制造生产率。 空气过滤装置可以包括具有联接到空气供应管线的开口孔的框架。 被构造成插入到框架中的缓冲框架可以包括多个狭槽部分，每个狭槽部分具有多个空气进/出孔，空气可以通过空气进入或离开缓冲器框架。 多个过滤器可以可释放地紧固到多个槽部分，以过滤包含在流过空气进/出孔的空气中的污染物质。 当更换多个过滤器时，可以使用用于中断通过空气入口/出口的空气的空气断路器，从而在更换期间向半导体制造装置提供净化的空气。

公开(公告)号：US07777273B2

公开(公告)日：2010-08-17

申请号：US11748973

申请日：2007-05-15

申请人： Ji-Young Kim

发明人： Ji-Young Kim

IPC分类号： H01L29/94 ,  H01L29/76 ,  H01L31/062 ,  H01L31/119 ,  H01L31/113

CPC分类号： H01L29/78 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/66621

摘要： A MOSFET having a recessed channel and a method of fabricating the same. The critical dimension (CD) of a recessed trench defining the recessed channel in a semiconductor substrate is greater than the CD of the gate electrode disposed on the semiconductor substrate. As a result, the misalignment margin for a photolithographic process used to form the gate electrodes can be increased, and both overlap capacitance and gate induced drain leakage (GIDL) can be reduced.

摘要翻译： 具有凹陷通道的MOSFET及其制造方法。 在半导体衬底中限定凹陷通道的凹槽的临界尺寸（CD）大于设置在半导体衬底上的栅电极的CD。 结果，可以增加用于形成栅电极的光刻工艺的未对准余量，并且可以减小重叠电容和栅极感应漏极泄漏（GIDL）。

公开(公告)号：US07709346B2

公开(公告)日：2010-05-04

申请号：US11624905

申请日：2007-01-19

申请人： Yong-Jin Kim ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Hyoung-Sub Kim ,  Mybong-Cheol Kim ,  Tae-Rin Chung ,  Sung-Hoon Chung ,  Ji-Young Kim

发明人： Yong-Jin Kim ,  Kyeong-Koo Chi ,  Chang-Jin Kang ,  Hyoung-Sub Kim ,  Mybong-Cheol Kim ,  Tae-Rin Chung ,  Sung-Hoon Chung ,  Ji-Young Kim

IPC分类号： H01L21/76

CPC分类号： H01L29/66621 ,  H01L21/823437 ,  H01L27/10876 ,  H01L29/7834

摘要： A semiconductor device includes a plurality of gate trenches, each of which has first inner walls, which face each other in a first direction which is perpendicular to a second direction in which active regions extend, and second inner walls, which face each other in the second direction in which the active regions extends. An isolation layer contacts a gate insulating layer throughout the entire length of the first inner walls of the gate trenches including from entrance portions of the gate trenches to bottom portions of the gate trenches, and a plurality of channel regions are disposed adjacent to the gate insulating layers in the semiconductor substrate along the second inner walls and the bottom portions of the gate trenches.

摘要翻译： 半导体器件包括多个栅极沟槽，每个栅极沟槽具有第一内壁，该第一内壁沿与第一方向相对的第一方向，该第一方向垂直于有源区域延伸的第二方向;以及第二内壁， 活动区域延伸的第二方向。 隔离层在包括从栅极沟槽的入口部分到栅极沟槽的底部的栅极沟槽的整个长度的整个长度上接触栅极绝缘层，并且多个沟道区域邻近栅极绝缘体 沿着第二内壁和栅极沟槽的底部的半导体衬底中的层。

公开(公告)号：US20090111232A1

公开(公告)日：2009-04-30

申请号：US12343035

申请日：2008-12-23

申请人： Hyun-Ki Kim ,  Jung-Hwa Lee ,  Ji-Young Kim

发明人： Hyun-Ki Kim ,  Jung-Hwa Lee ,  Ji-Young Kim

IPC分类号： H01L21/762

CPC分类号： H01L29/945 ,  H01L27/0207 ,  H01L27/0805 ,  H01L27/10861 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/66181 ,  H01L29/66621 ,  H01L29/78

摘要： A semiconductor device having a decoupling capacitor and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate having a cell region, a first peripheral circuit region, and a second peripheral circuit region. At least one channel trench is disposed in the cell region of the semiconductor substrate. At least one first capacitor trench is disposed in the first peripheral circuit region of the semiconductor substrate, and at least one second capacitor trench is disposed in the second peripheral circuit region of the semiconductor substrate. A gate electrode is disposed in the cell region of the semiconductor substrate and fills the channel trench. A first upper electrode is disposed in the first peripheral circuit region of the semiconductor substrate and fills at least the first capacitor trench. A second upper electrode is disposed in the second peripheral circuit region of the semiconductor substrate and fills at least the second capacitor trench. A gate dielectric layer is interposed between the channel trench and the gate electrode. A first dielectric layer is interposed between the semiconductor substrate of the first peripheral circuit region having the first capacitor trench and the first upper electrode and has the same thickness as the gate dielectric layer. A second dielectric layer is interposed between the semiconductor substrate of the second peripheral circuit region having the second capacitor trench and the second upper electrode and has a different thickness from the first dielectric layer.

摘要翻译： 提供具有去耦电容器的半导体器件及其制造方法。 半导体器件包括具有单元区域，第一外围电路区域和第二外围电路区域的半导体衬底。 至少一个通道沟槽设置在半导体衬底的单元区域中。 至少一个第一电容器沟槽设置在半导体衬底的第一外围电路区域中，并且至少一个第二电容器沟槽设置在半导体衬底的第二外围电路区域中。 栅电极设置在半导体衬底的单元区域中并填充沟槽。 第一上电极设置在半导体衬底的第一外围电路区域中，并且填充至少第一电容器沟槽。 第二上电极设置在半导体衬底的第二外围电路区域中，并且填充至少第二电容器沟槽。 栅极电介质层介于通道沟槽和栅电极之间。 在具有第一电容器沟槽的第一外围电路区域的半导体衬底和第一上电极之间插入第一电介质层，并且具有与栅极电介质层相同的厚度。 在具有第二电容器沟槽的第二外围电路区域的半导体衬底和第二上部电极之间插入第二电介质层，并且具有与第一电介质层不同的厚度。

公开(公告)号：US07485911B2

公开(公告)日：2009-02-03

申请号：US11449959

申请日：2006-06-09

申请人： Hyun-Ki Kim ,  Jung-Hwa Lee ,  Ji-Young Kim

发明人： Hyun-Ki Kim ,  Jung-Hwa Lee ,  Ji-Young Kim

IPC分类号： H01L27/108 ,  H01L29/76

CPC分类号： H01L29/945 ,  H01L27/0207 ,  H01L27/0805 ,  H01L27/10861 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/66181 ,  H01L29/66621 ,  H01L29/78

摘要： A semiconductor device having a decoupling capacitor and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate having a cell region, a first peripheral circuit region, and a second peripheral circuit region. At least one channel trench is disposed in the cell region of the semiconductor substrate. At least one first capacitor trench is disposed in the first peripheral circuit region of the semiconductor substrate, and at least one second capacitor trench is disposed in the second peripheral circuit region of the semiconductor substrate. A gate electrode is disposed in the cell region of the semiconductor substrate and fills the channel trench. A first upper electrode is disposed in the first peripheral circuit region of the semiconductor substrate and fills at least the first capacitor trench. A second upper electrode is disposed in the second peripheral circuit region of the semiconductor substrate and fills at least the second capacitor trench. A gate dielectric layer is interposed between the channel trench and the gate electrode. A first dielectric layer is interposed between the semiconductor substrate of the first peripheral circuit region having the first capacitor trench and the first upper electrode and has the same thickness as the gate dielectric layer. A second dielectric layer is interposed between the semiconductor substrate of the second peripheral circuit region having the second capacitor trench and the second upper electrode and has a different thickness from the first dielectric layer.

摘要翻译： 提供具有去耦电容器的半导体器件及其制造方法。 半导体器件包括具有单元区域，第一外围电路区域和第二外围电路区域的半导体衬底。 至少一个通道沟槽设置在半导体衬底的单元区域中。 至少一个第一电容器沟槽设置在半导体衬底的第一外围电路区域中，并且至少一个第二电容器沟槽设置在半导体衬底的第二外围电路区域中。 栅电极设置在半导体衬底的单元区域中并填充沟槽。 第一上电极设置在半导体衬底的第一外围电路区域中，并且填充至少第一电容器沟槽。 第二上电极设置在半导体衬底的第二外围电路区域中，并填充至少第二电容器沟槽。 栅极电介质层介于通道沟槽和栅电极之间。 在具有第一电容器沟槽的第一外围电路区域的半导体衬底和第一上电极之间插入第一电介质层，并且具有与栅极电介质层相同的厚度。 在具有第二电容器沟槽的第二外围电路区域的半导体衬底和第二上部电极之间插入第二电介质层，并且具有与第一电介质层不同的厚度。

公开(公告)号：US20090001352A1

公开(公告)日：2009-01-01

申请号：US12056374

申请日：2008-03-27

申请人： Jeong-hee Han ,  Ji-Young Kim ,  Chung-woo Kim ,  Kang Long Wang ,  Siguang Ma

发明人： Jeong-hee Han ,  Ji-Young Kim ,  Chung-woo Kim ,  Kang Long Wang ,  Siguang Ma

IPC分类号： H01L29/12 ,  H01L29/792 ,  H01L21/336

CPC分类号： H01L29/792 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7926 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2924/01019 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00012

摘要： Provided is a non-volatile memory device that can be highly integrated and may have a high reliability. Some embodiments of the non-volatile memory device include a first doping layer having a first conductivity on a substrate, a semiconductor pillar extending from the first doping layer on the substrate in an upward direction and having second conductivity opposite to the first conductivity, and a control gate electrode surrounding a sidewall of the semiconductor pillar. Embodiments of the non-volatile memory device may include a charge storage layer interposed between the semiconductor pillar and the control gate electrode and a second doping layer of the first conductivity that is disposed on the semiconductor pillar and is electrically connected to the semiconductor pillar.

摘要翻译： 提供了可以高度集成并且可能具有高可靠性的非易失性存储器件。 非易失性存储器件的一些实施例包括在衬底上具有第一导电性的第一掺杂层，从衬底上的第一掺杂层向上方延伸并且具有与第一导电性相反的第二导电性的半导体柱，以及 围绕半导体柱的侧壁的控制栅电极。 非易失性存储器件的实施例可以包括插入在半导体柱和控制栅电极之间的电荷存储层和设置在半导体柱上并与半导体柱电连接的第一导电性的第二掺杂层。

公开(公告)号：US07362531B2

公开(公告)日：2008-04-22

申请号：US11324227

申请日：2006-01-04

申请人： Ji-Young Kim

发明人： Ji-Young Kim

IPC分类号： G11B19/02

CPC分类号： G11B5/54 ,  G11B5/5582 ,  G11B19/04 ,  G11B19/08

摘要： A portable wireless communication terminal includes a sensor to detect a movement of the portable wireless communication terminal and output a first signal based on an acceleration of the movement and a second signal based on a velocity of the movement and a controller to control a hard disk drive (HDD) in response to both the first and second signals.

摘要翻译： 便携式无线通信终端包括：传感器，用于检测便携式无线通信终端的移动，并基于移动的加速度输出第一信号;基于移动速度输出第二信号;以及控制器，用于控制硬盘驱动器 （HDD）响应于第一和第二信号。