公开(公告)号：US20090001352A1

公开(公告)日：2009-01-01

申请号：US12056374

申请日：2008-03-27

申请人： Jeong-hee Han ,  Ji-Young Kim ,  Chung-woo Kim ,  Kang Long Wang ,  Siguang Ma

发明人： Jeong-hee Han ,  Ji-Young Kim ,  Chung-woo Kim ,  Kang Long Wang ,  Siguang Ma

IPC分类号： H01L29/12 ,  H01L29/792 ,  H01L21/336

CPC分类号： H01L29/792 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7926 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2924/01019 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00012

摘要： Provided is a non-volatile memory device that can be highly integrated and may have a high reliability. Some embodiments of the non-volatile memory device include a first doping layer having a first conductivity on a substrate, a semiconductor pillar extending from the first doping layer on the substrate in an upward direction and having second conductivity opposite to the first conductivity, and a control gate electrode surrounding a sidewall of the semiconductor pillar. Embodiments of the non-volatile memory device may include a charge storage layer interposed between the semiconductor pillar and the control gate electrode and a second doping layer of the first conductivity that is disposed on the semiconductor pillar and is electrically connected to the semiconductor pillar.

摘要翻译： 提供了可以高度集成并且可能具有高可靠性的非易失性存储器件。 非易失性存储器件的一些实施例包括在衬底上具有第一导电性的第一掺杂层，从衬底上的第一掺杂层向上方延伸并且具有与第一导电性相反的第二导电性的半导体柱，以及 围绕半导体柱的侧壁的控制栅电极。 非易失性存储器件的实施例可以包括插入在半导体柱和控制栅电极之间的电荷存储层和设置在半导体柱上并与半导体柱电连接的第一导电性的第二掺杂层。

公开(公告)号：US20090001419A1

公开(公告)日：2009-01-01

申请号：US12056383

申请日：2008-03-27

申请人： Jeong-hee Han ,  Ji-young Kim ,  Kang Lung Wang ,  Chung-woo Kim ,  Soo-doo Chae ,  Chan-jin Park

发明人： Jeong-hee Han ,  Ji-young Kim ,  Kang Lung Wang ,  Chung-woo Kim ,  Soo-doo Chae ,  Chan-jin Park

IPC分类号： H01L29/778 ,  H01L29/792 ,  H01L21/336

CPC分类号： H01L27/115 ,  B82Y10/00 ,  H01L27/0688 ,  H01L27/11517 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/40114 ,  H01L29/40117

摘要： Provided are non-volatile memory devices that may realize high integration and have high reliability. A plurality of first semiconductor layers are stacked on a substrate. A plurality of second semiconductor layers are interposed between the plurality of first semiconductor layers, respectively, and are recessed from one end of each of the plurality of first semiconductor layers to define a plurality of first trenches between the plurality of first semiconductor layers. A plurality of first storage nodes are provided on surfaces of the second semiconductor layers inside the plurality of first trenches. Devices may include a plurality of first control gate electrodes that are formed on the plurality of first storage nodes to fill the plurality of first trenches.

摘要翻译： 提供可以实现高集成度并且具有高可靠性的非易失性存储器件。 多个第一半导体层堆叠在基板上。 多个第二半导体层分别插入在多个第一半导体层之间，并且从多个第一半导体层的每一个的一端凹入以在多个第一半导体层之间限定多个第一沟槽。 多个第一存储节点设置在多个第一沟槽内的第二半导体层的表面上。 器件可以包括形成在多个第一存储节点上以填充多个第一沟槽的多个第一控制栅电极。

公开(公告)号：US20090181531A1

公开(公告)日：2009-07-16

申请号：US12346934

申请日：2008-12-31

申请人： Soo-doo Chae ,  Chung-woo Kim ,  Choong-man Lee ,  Yung-hee Lee ,  Chan-jin Park ,  Sung-wook Hwang ,  Jeong-hee Han ,  Do-haing Lee ,  Jin-seok Lee

发明人： Soo-doo Chae ,  Chung-woo Kim ,  Choong-man Lee ,  Yung-hee Lee ,  Chan-jin Park ,  Sung-wook Hwang ,  Jeong-hee Han ,  Do-haing Lee ,  Jin-seok Lee

IPC分类号： H01L21/28

CPC分类号： H01L21/31155 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792

摘要： Methods of manufacturing non-volatile memory devices that can reduce or prevent loss of charges stored in a charge storage layer and/or that can improve charge storage capacity by neutral beam irradiation of an insulating layer are disclosed. The methods include forming a tunneling insulating layer on a substrate, forming a charge storage layer on the tunneling insulating layer, forming a blocking insulating layer on the charge storage layer, irradiating the blocking insulating layer and/or the tunneling insulating layer with a neutral beam, and forming a gate conductive layer on the blocking insulating layer.

摘要翻译： 公开了制造可以减少或防止存储在电荷存储层中的电荷损失和/或可通过绝缘层的中性束照射改善电荷存储容量的非易失性存储器件的制造方法。 所述方法包括在衬底上形成隧道绝缘层，在隧道绝缘层上形成电荷存储层，在电荷存储层上形成阻挡绝缘层，用中性光束照射阻挡绝缘层和/或隧道绝缘层 并且在所述阻挡绝缘层上形成栅极导电层。

公开(公告)号：US20080087940A1

公开(公告)日：2008-04-17

申请号：US11589994

申请日：2006-10-31

申请人： Soo-doo Chae ,  Chung-woo Kim ,  Chan-jin Park ,  Jeong-hee Han ,  Byung-gook Park ,  Il-han Park

发明人： Soo-doo Chae ,  Chung-woo Kim ,  Chan-jin Park ,  Jeong-hee Han ,  Byung-gook Park ,  Il-han Park

IPC分类号： H01L29/792 ,  H01L21/8238

CPC分类号： H01L29/792 ,  H01L29/66833 ,  H01L29/7926

摘要： A nonvolatile memory device, includes a semiconductor substrate having a bottom part, a second vertical part positioned vertically on the bottom part, and a first vertical part having a width smaller than a width of the second vertical part and positioned on the second vertical part to have a boundary step therebetween; a charge trap layer disposed on a lateral surface of the first vertical part and on an upper surface of the boundary step; and a control gate electrode disposed on an upper surface of the bottom part and on lateral surfaces of the second vertical part and the charge trap layer.

摘要翻译： 一种非易失性存储器件，包括：半导体衬底，具有底部;垂直于第二垂直方向的底部;以及第一垂直部分，其宽度小于第二垂直部分的宽度，并且位于第二垂直部分上， 在其间具有边界步骤; 电荷陷阱层，设置在所述第一垂直部分的侧表面和所述边界台阶的上表面上; 以及设置在所述底部的上表面和所述第二垂直部分和所述电荷陷阱层的侧表面上的控制栅电极。

公开(公告)号：US20060118858A1

公开(公告)日：2006-06-08

申请号：US11246114

申请日：2005-10-11

申请人： Sang-hun Jeon ,  Jeong-hee Han ,  Chung-woo Kim

发明人： Sang-hun Jeon ,  Jeong-hee Han ,  Chung-woo Kim

IPC分类号： H01L29/788

CPC分类号： H01L29/513 ,  G11C16/0416 ,  G11C16/0466 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/7881 ,  H01L29/792

摘要： A non-volatile semiconductor memory device comprises a substrate including a source region, a drain region and a channel region provided between the source region and the drain region with a gate stack located above the channel region with a metal gate located above the gate stack. The metal gate is comprised of a metal having a specific metal work function relative to a composition of a layer of the gate stack that causes electrons to travel through the entire thickness of the blocking layer via direct tunneling. The gate stack preferably comprises a multiple layer stack selected from a group of multiple layer stacks consisting of: ONO, ONH, OHH, OHO, HHH, or HNH, where O is an oxide material, N is SiN, and H is a high κ material.

摘要翻译： 非易失性半导体存储器件包括：衬底，其包括源区域，漏极区域和设置在源极区域和漏极区域之间的沟道区域，栅极堆叠位于沟道区域上方，金属栅极位于栅极叠层之上。 金属栅极由具有特定的金属功函数的金属组成，相对于栅堆叠层的组成，其使电子通过直接隧道穿过阻挡层的整个厚度。 栅极堆叠优选地包括选自由以下组成的多层堆叠的多层堆叠：ONO，ONH，OHH，OHO，HHH或HNH，其中O是氧化物材料，N是SiN，H是高kappa 材料。

公开(公告)号：US07391075B2

公开(公告)日：2008-06-24

申请号：US11246114

申请日：2005-10-11

申请人： Sang-hun Jeon ,  Jeong-hee Han ,  Chung-woo Kim

发明人： Sang-hun Jeon ,  Jeong-hee Han ,  Chung-woo Kim

IPC分类号： H01L29/788

CPC分类号： H01L29/513 ,  G11C16/0416 ,  G11C16/0466 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/7881 ,  H01L29/792

摘要： A non-volatile semiconductor memory device comprises a substrate including a source region, a drain region and a channel region provided between the source region and the drain region with a gate stack located above the channel region with a metal gate located above the gate stack. The metal gate is comprised of a metal having a specific metal work function relative to a composition of a layer of the gate stack that causes electrons to travel through the entire thickness of the blocking layer via direct tunneling. The gate stack preferably comprises a multiple layer stack selected from a group of multiple layer stacks consisting of: ONO, ONH, OHH, OHO, HHH, or HNH, where O is an oxide material, N is SiN, and H is a high κ material.

摘要翻译： 非易失性半导体存储器件包括：衬底，其包括源区域，漏极区域和设置在源极区域和漏极区域之间的沟道区域，栅极堆叠位于沟道区域上方，金属栅极位于栅极叠层之上。 金属栅极由具有特定的金属功函数的金属组成，相对于栅堆叠层的组成，其使电子通过直接隧道穿过阻挡层的整个厚度。 栅极堆叠优选地包括选自由以下组成的多层堆叠的多层堆叠：ONO，ONH，OHH，OHO，HHH或HNH，其中O是氧化物材料，N是SiN，H是高kappa 材料。

公开(公告)号：US20080272426A1

公开(公告)日：2008-11-06

申请号：US12060391

申请日：2008-04-01

申请人： Soo Doo Chae ,  Chung-woo Kim ,  Chan-jin Park ,  Jeong-hee Han ,  Byung-gook Park ,  Gil-seong Lee

发明人： Soo Doo Chae ,  Chung-woo Kim ,  Chan-jin Park ,  Jeong-hee Han ,  Byung-gook Park ,  Gil-seong Lee

IPC分类号： H01L29/00 ,  H01L21/336

CPC分类号： H01L29/1037 ,  H01L21/28132 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/66787 ,  H01L29/7887 ,  H01L29/7923 ,  H01L29/7926

摘要： Nonvolatile memory transistors including active pillars having smooth side surfaces with an acute inward angle are provided. The transistor has an active pillar having smooth side surfaces with an acute inward angle and protrudes from semiconductor substrate. A gate electrode surrounds the side surfaces of the active pillar. A charge storage layer is provided between the active pillar and the gate electrode. Nonvolatile memory arrays including the transistor and related methods of fabrication are also provided.

摘要翻译： 提供了包括具有锐角内角的平滑侧表面的活动柱的非易失性存储晶体管。 该晶体管具有活性柱，其具有具有锐角内角的平滑侧表面并从半导体衬底突出。 栅电极围绕有源柱的侧表面。 电荷存储层设置在有源支柱和栅电极之间。 还提供了包括晶体管和相关制造方法的非易失性存储器阵列。

公开(公告)号：US07402492B2

公开(公告)日：2008-07-22

申请号：US11385642

申请日：2006-03-21

申请人： Sang-hun Jeon ,  Kyu-sik Kim ,  Chung-woo Kim ,  Sung-ho Park ,  Yo-sep Min ,  Jeong-hee Han

发明人： Sang-hun Jeon ,  Kyu-sik Kim ,  Chung-woo Kim ,  Sung-ho Park ,  Yo-sep Min ,  Jeong-hee Han

IPC分类号： H01L21/336

CPC分类号： H01L21/324 ,  H01L21/28273 ,  H01L21/28282

摘要： In a method of manufacturing a memory device having improved erasing characteristics, the method includes sequentially forming a tunneling oxide layer, a charge storing layer, and a blocking oxide layer on a semiconductor substrate; annealing the semiconductor substrate including the tunneling oxide layer, the charge storing layer, and the blocking oxide layer under a gas atmosphere so that the blocking oxide layer has a negative fixed oxide charge; forming a gate electrode on the blocking oxide layer with the negative fixed oxide charge and etching the tunneling oxide layer, the charge storing layer, and the blocking oxide layer to form a gate structure; and forming a first doped region and a second doped region in the semiconductor substrate at sides of the gate structure by doping the semiconductor substrate with a dopant.

摘要翻译： 在制造具有改善的擦除特性的存储器件的方法中，该方法包括在半导体衬底上依次形成隧穿氧化物层，电荷存储层和阻挡氧化物层; 在气体气氛下退火包括隧道氧化物层，电荷存储层和阻挡氧化物层的半导体衬底，使得阻挡氧化物层具有负的固定氧化物电荷; 在阻挡氧化物层上形成具有负固定氧化物电荷的栅电极，蚀刻隧道氧化物层，电荷存储层和阻挡氧化物层以形成栅极结构; 以及通过用掺杂剂掺杂半导体衬底，在栅极结构的侧面在半导体衬底中形成第一掺杂区和第二掺杂区。

公开(公告)号：US20060211205A1

公开(公告)日：2006-09-21

申请号：US11385642

申请日：2006-03-21

申请人： Sang-hun Jeon ,  Kyu-sik Kim ,  Chung-woo Kim ,  Sung-ho Park ,  Yo-sep Min ,  Jeong-hee Han

发明人： Sang-hun Jeon ,  Kyu-sik Kim ,  Chung-woo Kim ,  Sung-ho Park ,  Yo-sep Min ,  Jeong-hee Han

IPC分类号： H01L21/336

CPC分类号： H01L21/324 ,  H01L21/28273 ,  H01L21/28282

摘要： In a method of manufacturing a memory device having improved erasing characteristics, the method includes sequentially forming a tunneling oxide layer, a charge storing layer, and a blocking oxide layer on a semiconductor substrate; annealing the semiconductor substrate including the tunneling oxide layer, the charge storing layer, and the blocking oxide layer under a gas atmosphere so that the blocking oxide layer has a negative fixed oxide charge; forming a gate electrode on the blocking oxide layer with the negative fixed oxide charge and etching the tunneling oxide layer, the charge storing layer, and the blocking oxide layer to form a gate structure; and forming a first doped region and a second doped region in the semiconductor substrate at sides of the gate structure by doping the semiconductor substrate with a dopant.

摘要翻译： 在制造具有改善的擦除特性的存储器件的方法中，该方法包括在半导体衬底上依次形成隧穿氧化物层，电荷存储层和阻挡氧化物层; 在气体气氛下退火包括隧道氧化物层，电荷存储层和阻挡氧化物层的半导体衬底，使得阻挡氧化物层具有负的固定氧化物电荷; 在阻挡氧化物层上形成具有负固定氧化物电荷的栅电极，蚀刻隧道氧化物层，电荷存储层和阻挡氧化物层以形成栅极结构; 以及通过用掺杂剂掺杂半导体衬底，在栅极结构的侧面在半导体衬底中形成第一掺杂区和第二掺杂区。

公开(公告)号：US07349262B2

公开(公告)日：2008-03-25

申请号：US11432375

申请日：2006-05-12

申请人： Youn-seok Jeong ,  Chung-woo Kim ,  Hee-soon Chae ,  Ju-hyung Kim ,  Jeong-hee Han ,  Jae-woong Hyun

发明人： Youn-seok Jeong ,  Chung-woo Kim ,  Hee-soon Chae ,  Ju-hyung Kim ,  Jeong-hee Han ,  Jae-woong Hyun

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/0466 ,  G11C16/04 ,  G11C29/50 ,  G11C29/50004

摘要： A method of programming a silicon oxide nitride oxide semiconductor (SONOS) memory device is provided. The SONOS memory device includes a substrate, first and second impurity regions spaced apart on the substrate, a gate oxide layer formed over the substrate between the first and second impurity regions, a trap layer formed over the gate oxide layer, an insulation layer formed over the trap layer, and a gate electrode formed over the insulation layer. The method of programming the SONOS device includes writing data into the SONOS memory device by applying a first voltage to the first impurity region, a gate voltage to the gate electrode, and a second voltage to the second impurity region, where the second voltage is a negative voltage.

摘要翻译： 提供了一种编程氧化硅氮氧化物半导体（SONOS）存储器件的方法。 SONOS存储器件包括衬底，在衬底上间隔开的第一和第二杂质区，在第一和第二杂质区之间的衬底上形成的栅氧化层，在栅极氧化物层上形成的阱层，形成在绝缘层上的绝缘层 陷阱层和形成在绝缘层上的栅电极。 对SONOS设备进行编程的方法包括：通过向第一杂质区施加第一电压，向栅电极施加第一电压，向第二杂质区施加第二电压，将数据写入SONOS存储器件，其中第二电压为 负电压。