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    Hybrid CMOS Technology With Nanowire Devices and Double Gated Planar Devices
    91.
    发明申请
    Hybrid CMOS Technology With Nanowire Devices and Double Gated Planar Devices 有权
    混合CMOS技术与纳米线器件和双门控平面器件

    公开(公告)号：US20130026451A1

    公开(公告)日：2013-01-31

    申请号：US13605076

    申请日：2012-09-06

    申请人： Sarunya Bangsaruntip ,  Josephine B. Chang ,  Leland Chang ,  Jeffrey W. Sleight

    发明人： Sarunya Bangsaruntip ,  Josephine B. Chang ,  Leland Chang ,  Jeffrey W. Sleight

    IPC分类号： H01L29/775

    CPC分类号： H01L29/775 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/513 ,  H01L29/66439 ,  H01L29/66772 ,  H01L29/78648 ,  H01L29/78696

    摘要： A substrate includes a first source region and a first drain region each having a first semiconductor layer disposed on a second semiconductor layer and a surface parallel to {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes; nanowire channel members suspended by the first source region and the first drain region, where the nanowire channel members include the first semiconductor layer, and opposing sidewall surfaces parallel to {100} crystalline planes and opposing faces parallel to the {110} crystalline planes. The substrate further includes a second source and drain regions having the characteristics of the first source and drain regions, and a single channel member suspended by the second source region and the second drain region and having the same characteristics as the nanowire channel members. A width of the single channel member is at least several times a width of a single nanowire member.

    摘要翻译： 衬底包括第一源极区域和第一漏极区域，每个第一漏极区域具有设置在第二半导体层上的第一半导体层和平行于{110}晶面的平面和平行于{110}晶面的相对侧壁表面的表面; 纳米线通道部件由第一源极区域和第一漏极区域悬挂，其中纳米线通道构件包括第一半导体层，以及平行于{100}晶面的相对侧壁表面和平行于{110}晶面的相对面。 衬底还包括具有第一源极和漏极区域的特性的第二源极和漏极区域以及由第二源极区域和第二漏极区域悬置并且具有与纳米线通道构件相同的特性的单个沟道构件。 单通道构件的宽度是单个纳米线构件的宽度的至少几倍。

    STRUCTURE FOR USE IN FABRICATION OF PIN HETEROJUNCTION TFET
    93.
    发明申请
    STRUCTURE FOR USE IN FABRICATION OF PIN HETEROJUNCTION TFET 审中-公开
    用于制造PIN异构TFET的结构

    公开(公告)号：US20120298963A1

    公开(公告)日：2012-11-29

    申请号：US13571392

    申请日：2012-08-10

    申请人： Sarunya Bangsaruntip ,  Steven Koester ,  Isaac Lauer ,  Jeffrey W. Sleight

    发明人： Sarunya Bangsaruntip ,  Steven Koester ,  Isaac Lauer ,  Jeffrey W. Sleight

    IPC分类号： H01L29/772

    CPC分类号： H01L29/7391 ,  H01L21/2007 ,  H01L21/76254 ,  H01L29/66227

    摘要： A structure for use in fabrication of a PiN heterojunction tunnel field effect transistor (TFET) includes a silicon wafer comprising an alignment trench, a p-type silicon germanium (SiGe) region, and a hydrogen implantation region underneath the p-type SiGe region and the alignment trench that divides the silicon wafer into a upper silicon region and a lower silicon region, wherein the upper silicon region comprises the alignment trench and the p-type SiGe region; and a first oxide layer located over the alignment trench and the p-type SiGe region that fills the alignment trench and is bonded to a second oxide layer located on a handle wafer; wherein the alignment trench is configured to align a wiring level of the device comprising the PiN heterojunction TFET to the p-type SiGe region.

    摘要翻译： 用于制造PiN异质结隧道场效应晶体管（TFET）的结构包括：硅晶片，其包括对准沟槽，p型硅锗（SiGe）区域和p型SiGe区域下方的氢注入区域，以及 所述对准沟槽将所述硅晶片分成上硅区域和下硅区域，其中所述上硅区域包括所述对准沟槽和所述p型SiGe区域; 以及位于对准沟槽和p型SiGe区域上方的第一氧化物层，其填充对准沟槽并且结合到位于处理晶片上的第二氧化物层; 其中所述对准沟槽被配置为将包括所述PiN异质结TFET的器件的布线电平对准到所述p型SiGe区域。

    Contacts for Nanowire Field Effect Transistors
    94.
    发明申请
    Contacts for Nanowire Field Effect Transistors 失效
    纳米线场效应晶体管的接触

    公开(公告)号：US20120280205A1

    公开(公告)日：2012-11-08

    申请号：US13551995

    申请日：2012-07-18

    申请人： Sarunya Bangsaruntip ,  Guy M. Cohen ,  Shreesh Narasimha ,  Jeffrey W. Sleight

    发明人： Sarunya Bangsaruntip ,  Guy M. Cohen ,  Shreesh Narasimha ,  Jeffrey W. Sleight

    IPC分类号： H01L29/775 ,  B82Y99/00

    CPC分类号： H01L29/0673 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823412 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696 ,  Y10S977/938

    摘要： A nanowire field effect transistor (FET) device includes a channel region including a silicon nanowire portion having a first distal end extending from the channel region and a second distal end extending from the channel region, the silicon portion is partially surrounded by a gate stack disposed circumferentially around the silicon portion, a source region including the first distal end of the silicon nanowire portion, a drain region including the second distal end of the silicon nanowire portion, a metallic layer disposed on the source region and the drain region, a first conductive member contacting the metallic layer of the source region, and a second conductive member contacting the metallic layer of the drain region.

    摘要翻译： 纳米线场效应晶体管（FET）器件包括沟道区域，该沟道区域包括具有从沟道区域延伸的第一远端的硅纳米线部分和从沟道区域延伸的第二远端，硅部分被设置的栅极堆叠部分地包围 围绕硅部分周向地包括包括硅纳米线部分的第一远端的源极区域，包括硅纳米线部分的第二远端的漏极区域，设置在源极区域和漏极区域上的金属层，第一导电 与源极区域的金属层接触的构件和与漏极区域的金属层接触的第二导电构件。

    NANOWIRE FET WITH TRAPEZOID GATE STRUCTURE
    99.
    发明申请
    NANOWIRE FET WITH TRAPEZOID GATE STRUCTURE 有权
    纳米结构的栅极结构

    公开(公告)号：US20110315950A1

    公开(公告)日：2011-12-29

    申请号：US12824293

    申请日：2010-06-28

    申请人： Jeffrey W. Sleight ,  Sarunya Bangsaruntip ,  Sebastian U. Engelmann ,  Ying Zhang

    发明人： Jeffrey W. Sleight ,  Sarunya Bangsaruntip ,  Sebastian U. Engelmann ,  Ying Zhang

    IPC分类号： H01L29/775 ,  H01L21/335

    CPC分类号： H01L29/775 ,  B82Y10/00 ,  H01L29/4232 ,  H01L29/513 ,  H01L29/66439

    摘要： In one embodiment, a method of providing a nanowire semiconductor device is provided, in which the gate structure to the nanowire semiconductor device has a trapezoid shape. The method may include forming a trapezoid gate structure surrounding at least a portion of a circumference of a nanowire. The first portion of the trapezoid gate structure that is in direct contact with an upper surface of the nanowire has a first width and a second portion of the trapezoid gate structure that is in direct contact with a lower surface of the nanowire has a second width. The second width of the trapezoid gate structure is greater than the first width of the trapezoid gate structure. The exposed portions of the nanowire that are adjacent to the portion of the nanowire that the trapezoid gate structure is surrounding are then doped to provide source and drain regions.

    摘要翻译： 在一个实施例中，提供了一种提供纳米线半导体器件的方法，其中对纳米线半导体器件的栅极结构具有梯形形状。 该方法可以包括形成围绕纳米线的圆周的至少一部分的梯形栅极结构。 与纳米线的上表面直接接触的梯形栅极结构的第一部分具有与纳米线的下表面直接接触的梯形栅极结构的第一宽度和第二部分具有第二宽度。 梯形栅极结构的第二宽度大于梯形栅极结构的第一宽度。 然后，与梯形栅极结构所围绕的部分纳米线相邻的纳米线的暴露部分被掺杂以提供源区和漏区。

    Nanowire Tunnel Field Effect Transistors
    100.
    发明申请
    Nanowire Tunnel Field Effect Transistors 有权
    纳米线隧道场效应晶体管

    公开(公告)号：US20110278546A1

    公开(公告)日：2011-11-17

    申请号：US12778315

    申请日：2010-05-12

    申请人： Sarunya Bangsaruntip ,  Isaac Lauer ,  Amlan Majumdar ,  Jeffrey W. Sleight

    发明人： Sarunya Bangsaruntip ,  Isaac Lauer ,  Amlan Majumdar ,  Jeffrey W. Sleight

    IPC分类号： H01L29/78 ,  H01L49/00

    CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696

    摘要： A method for forming a nanowire tunnel field effect transistor (FET) device includes forming a nanowire suspended by a first pad region and a second pad region, forming a gate around a portion of the nanowire, forming a protective spacer adjacent to sidewalls of the gate structure and around portions of the nanowire extending from the gate structure, implanting ions in a first portion of the exposed nanowire, removing a second portion of the exposed nanowire to form a cavity defined by the core portion of the nanowire surrounded by the gate structure and the spacer, exposing a silicon portion of the substrate, and epitaxially growing a doped semiconductor material in the cavity from exposed cross section of the nanowire, the second pad region, and the exposed silicon portion to connect the exposed cross sections of the nanowire to the second pad region.

    摘要翻译： 形成纳米线隧道场效应晶体管（FET）器件的方法包括形成由第一焊盘区域和第二焊盘区域悬挂的纳米线，在纳米线的一部分周围形成栅极，形成邻近栅极侧壁的保护隔离层 结构和纳米线的周围部分从栅极结构延伸，将离子注入暴露的纳米线的第一部分，去除暴露的纳米线的第二部分以形成由栅极结构包围的纳米线的核心部分限定的空腔;以及 所述间隔物暴露所述衬底的硅部分，以及从所述纳米线，所述第二焊盘区域和暴露的硅部分的暴露截面外延生长所述腔中的掺杂半导体材料，以将所述纳米线的暴露的横截面与 第二垫区域。