公开(公告)号：US20100291747A1

公开(公告)日：2010-11-18

申请号：US12843806

申请日：2010-07-26

申请人： Hsiang Lan Lung ,  Shih-Hung Chen

发明人： Hsiang Lan Lung ,  Shih-Hung Chen

IPC分类号： H01L21/02

CPC分类号： G11C13/0004 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1675 ,  H01L45/1691

摘要： A phase change memory device comprises a photolithographically formed phase change memory cell having first and second electrodes and a phase change element positioned between and electrically coupling the opposed contact elements of the electrodes to one another. The phase change element has a width, a length and a thickness. The length, the thickness and the width are less than a minimum photolithographic feature size of the process used to form the phase change memory cell. The size of the photoresist masks used in forming the memory cell may be reduced so that the length and the width of the phase change element are each less than the minimum photolithographic feature size.

摘要翻译： 相变存储器件包括具有第一和第二电极的光刻形成的相变存储器单元和位于彼此之间并将电极的相对接触元件彼此电耦合的相变元件。 相变元件具有宽度，长度和厚度。 长度，厚度和宽度小于用于形成相变存储器单元的工艺的最小光刻特征尺寸。 可以减小用于形成存储单元的光致抗蚀剂掩模的尺寸，使得相变元件的长度和宽度均小于最小光刻特征尺寸。

公开(公告)号：US20100264396A1

公开(公告)日：2010-10-21

申请号：US12426809

申请日：2009-04-20

申请人： Hsiang-Lan Lung ,  Shih-Hung Chen ,  Stephen M. Rossnagel

发明人： Hsiang-Lan Lung ,  Shih-Hung Chen ,  Stephen M. Rossnagel

IPC分类号： H01L47/00 ,  H01L21/283

CPC分类号： H01L45/142 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675

摘要： An electrode structure and a method for manufacturing an integrated circuit electrode includes forming a bottom electrode comprising a pipe-shaped member, filled with a conductive material such as n-doped silicon, and having a ring-shaped top surface. A disc-shaped insulating member is formed on the top of the pipe-shaped member by oxidizing the conductive fill. A layer of programmable resistance material, such as a phase change material, is deposited in contact with the top surface of the pipe-shaped member. A top electrode in contact with the layer of programmable resistance material.

摘要翻译： 电极结构和集成电路电极的制造方法包括形成包含管状部件的底部电极，该管状部件填充有诸如n掺杂硅的导电材料，并具有环形顶表面。 通过氧化导电填料，在管状构件的顶部上形成圆盘形的绝缘构件。 将一层可编程电阻材料（例如相变材料）沉积成与管状构件的顶表面接触。 与可编程电阻材料层接触的顶部电极。

公开(公告)号：US07688619B2

公开(公告)日：2010-03-30

申请号：US11612093

申请日：2006-12-18

申请人： Hsiang-Lan Lung ,  Rich Liu ,  Shih-Hung Chen ,  Yi-Chou Chen

发明人： Hsiang-Lan Lung ,  Rich Liu ,  Shih-Hung Chen ,  Yi-Chou Chen

IPC分类号： G11C11/00

CPC分类号： G11C8/10 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0028 ,  G11C2213/53 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/165 ,  H01L45/1675

摘要： A phase change memory cell includes first and second electrodes electrically coupled by a phase change element. At least a section of the phase change element comprises a higher reset transition temperature portion and a lower reset transition temperature portion. The lower reset transition temperature portion comprises a phase change region which can be transitioned, by the passage of electrical current therethrough, from generally crystalline to generally amorphous states at a lower temperature than the higher reset transition temperature portion. The phase change element may comprise an outer, generally tubular, higher reset transition temperature portion surrounding an inner, lower reset transition temperature portion.

摘要翻译： 相变存储单元包括由相变元件电耦合的第一和第二电极。 相变元件的至少一部分包括较高的复位转变温度部分和较低的复位转变温度部分。 下复位转变温度部分包括可以通过电流通过从相对于较高复位转变温度部分的较低温度的大致结晶到大致非晶状态的相变区域。 相变元件可以包括围绕内部，下部复位转变温度部分的外部，大体上管状的较高复位转变温度部分。

公开(公告)号：US07608503B2

公开(公告)日：2009-10-27

申请号：US11285473

申请日：2005-11-21

申请人： Hsiang Lan Lung ,  Shih-Hung Chen ,  Yi-Chou Chen

发明人： Hsiang Lan Lung ,  Shih-Hung Chen ,  Yi-Chou Chen

IPC分类号： H01L21/8242

CPC分类号： H01L27/112 ,  G11C2213/52 ,  H01L21/0337 ,  H01L21/0338 ,  H01L27/115 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/124 ,  H01L45/144 ,  H01L45/1691

摘要： A method of forming a memory cell comprises forming a stack comprising a first electrode, an insulating layer over the first electrode, and a second electrode over the insulating layer, with a side wall on the stack. A side wall spacer comprising a programmable resistive material in electrical communication with the first and second electrodes is formed. The side wall spacer is formed by depositing a layer of programmable resistive material over the side wall of the stack, anisotropically etching the layer of programmable resistive material to remove it in areas away from the side wall, and selectively etching the programmable resistive material according to a pattern to define the width of the side wall spacer. In embodiments described herein, the width is about 40 nanometers or less.

摘要翻译： 一种形成存储单元的方法包括：在叠层上形成包括第一电极，绝缘层上的绝缘层和绝缘层上的第二电极的堆叠。 形成包括与第一和第二电极电连通的可编程电阻材料的侧壁间隔物。 通过在堆叠的侧壁上沉积可编程电阻材料层来形成侧壁间隔物，各向异性地蚀刻可编程电阻材料层，以便在远离侧壁的区域中去除它，并根据所述方法选择性地蚀刻可编程电阻材料 用于限定侧壁间隔物的宽度的图案。 在本文所述的实施例中，宽度为约40纳米或更小。

公开(公告)号：US07423300B2

公开(公告)日：2008-09-09

申请号：US11420107

申请日：2006-05-24

申请人： Hsiang-Lan Lung ,  Rich Liu ,  Yi-Chou Chen ,  Shih-Hung Chen

发明人： Hsiang-Lan Lung ,  Rich Liu ,  Yi-Chou Chen ,  Shih-Hung Chen

IPC分类号： H01L27/10 ,  H01L29/73 ,  H01L23/58 ,  H01L27/148 ,  H01L29/768 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L45/144 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/148 ,  H01L2924/0002 ,  Y10S257/907 ,  H01L2924/00

摘要： A memory device. An array of memory elements is formed on a semiconductor chip. A parallel array of word lines extends in a first direction, connecting each memory element to a data source, and a parallel array of bit lines extends in a second direction, connecting each memory element to a data source, the second direction forming an acute angle to the first direction. The connection between each bit line and each memory element is a phase change element composed of memory material having at least two solid phases.

摘要翻译： 一个记忆体装置 存储元件阵列形成在半导体芯片上。 字线的并行阵列沿着第一方向延伸，将每个存储器元件连接到数据源，并行的位线阵列沿第二方向延伸，将每个存储器元件连接到数据源，第二方向形成锐角 到第一个方向。 每个位线与每个存储元件之间的连接是由具有至少两个固相的存储器材料组成的相变元件。

公开(公告)号：US07321130B2

公开(公告)日：2008-01-22

申请号：US11155067

申请日：2005-06-17

申请人： Hsiang Lan Lung ,  Shih-Hung Chen

发明人： Hsiang Lan Lung ,  Shih-Hung Chen

IPC分类号： H01L47/00 ,  G11C11/00

CPC分类号： H01L45/1226 ,  G11C13/0004 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1691

摘要： A memory device comprising a first electrode having a top side, a second electrode having a top side and an insulating member between the first electrode and the second electrode. The insulating member has a thickness between the first and second electrodes near the top side of the first electrode and the top side of the second electrode. A bridge of memory material crosses the insulating member, and defines an inter-electrode path between the first and second electrodes across the insulating member. An array of such memory cells is provided. In the array, a plurality of electrode members and insulating members therebetween comprise an electrode layer on an integrated circuit. The bridges of memory material have sub-lithographic dimensions.

摘要翻译： 一种存储器件，包括具有顶侧的第一电极，具有顶侧的第二电极和位于第一电极和第二电极之间的绝缘构件。 绝缘构件在第一电极的顶侧附近和第二电极的顶侧之间具有在第一和第二电极之间的厚度。 记忆材料桥跨越绝缘构件，并且在绝缘构件之间限定了第一和第二电极之间的电极间路径。 提供这样的存储单元阵列。 在阵列中，多个电极构件和绝缘构件包括集成电路上的电极层。 记忆材料的桥梁具有亚光刻尺寸。

公开(公告)号：US20070285960A1

公开(公告)日：2007-12-13

申请号：US11420107

申请日：2006-05-24

申请人： Hsiang-Lan Lung ,  Rich Liu ,  Yi-Chou Chen ,  Shih-Hung Chen

发明人： Hsiang-Lan Lung ,  Rich Liu ,  Yi-Chou Chen ,  Shih-Hung Chen

IPC分类号： G11C11/00

CPC分类号： H01L45/144 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/148 ,  H01L2924/0002 ,  Y10S257/907 ,  H01L2924/00

摘要： A memory device. An array of memory elements is formed on a semiconductor chip. A parallel array of word lines extends in a first direction, connecting each memory element to a data source, and a parallel array of bit lines extends in a second direction, connecting each memory element to a data source, the second direction forming an acute angle to the first direction. The connection between each bit line and each memory element is a phase change element composed of memory material having at least two solid phases.

摘要翻译： 一个记忆体装置 存储元件阵列形成在半导体芯片上。 字线的并行阵列沿着第一方向延伸，将每个存储器元件连接到数据源，并行的位线阵列沿第二方向延伸，将每个存储器元件连接到数据源，第二方向形成锐角 到第一个方向。 每个位线与每个存储元件之间的连接是由具有至少两个固相的存储器材料组成的相变元件。

公开(公告)号：US20070128870A1

公开(公告)日：2007-06-07

申请号：US11380988

申请日：2006-05-01

申请人： Shih-Hung Chen

发明人： Shih-Hung Chen

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/76877 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144 ,  H01L45/16

摘要： The surface topology of a plug surface area-containing surface of a semiconductor device can be improved by removing material to create a first planarized surface with at least one plug surface area, typically a tungsten or copper plug area, comprising a recessed region. A material is deposited onto the first planarized surface, to create a material layer, and into the upper portion of the recessed region. The material layer is removed to create a second planarized surface with the material maintained in the upper portion of the recessed region. To form a semiconductor phase change memory device, a phase change element is formed between the at least one plug area, acting as a first electrode, at the second planarized surface and a second electrode.

摘要翻译： 通过去除材料以形成具有包括凹陷区域的至少一个插塞表面区域（通常为钨或铜插塞区域）的第一平坦化表面，可以改善半导体器件的表面积的表面的表面拓扑。 将材料沉积到第一平坦化表面上，以形成材料层并进入凹陷区域的上部。 去除材料层以产生第二平坦化表面，其中材料保持在凹陷区域的上部。 为了形成半导体相变存储器件，在第二平坦化表面和第二电极之间的至少一个用作第一电极的插塞区域之间形成相变元件。

公开(公告)号：US20070121374A1

公开(公告)日：2007-05-31

申请号：US11459106

申请日：2006-07-21

申请人： Hsiang Lan Lung ,  Shih-Hung Chen

发明人： Hsiang Lan Lung ,  Shih-Hung Chen

IPC分类号： G11C11/00

CPC分类号： H01L45/144 ,  G11C13/0004 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1675 ,  H01L45/1691

摘要： A phase change memory device comprises a photolithographically formed phase change memory cell having first and second electrodes and a phase change bridge positioned between and electrically coupling the opposed sides of the electrodes to one another. The phase change bridge has a length, a width and a thickness. The width, the thickness and the length are less than a minimum photolithographic feature size of the process used to form the phase change memory cell. The size of the photoresist masks used in forming the memory cell may be reduced so that the width and the length of the phase change bridge are each less than the minimum photolithographic feature size.

摘要翻译： 相变存储器件包括具有第一和第二电极的光刻形成的相变存储器单元和位于电极的相对侧之间并将电极彼此电耦合的相变桥。 相变桥具有长度，宽度和厚度。 宽度，厚度和长度小于用于形成相变存储单元的工艺的最小光刻特征尺寸。 可以减小用于形成存储单元的光致抗蚀剂掩模的尺寸，使得相变桥的宽度和长度均小于最小光刻特征尺寸。

公开(公告)号：US20070054429A1

公开(公告)日：2007-03-08

申请号：US11161997

申请日：2005-08-25

申请人： Tsuan-Lun Lung ,  Chih-Hung Cheng ,  Yi-Tyng Wu ,  Shih-Hung Chen

发明人： Tsuan-Lun Lung ,  Chih-Hung Cheng ,  Yi-Tyng Wu ,  Shih-Hung Chen

IPC分类号： H01L51/40 ,  H01L21/00 ,  H01L21/44

CPC分类号： H01L51/5271 ,  G02F1/133553 ,  G02F1/136277 ,  H01L51/56 ,  H01L2251/5315

摘要： A method for manufacturing a back panel on a substrate is provided. The substrate has at least a switching device formed therein and a dielectric layer structure formed thereon. An interconnect structure is also formed in the dielectric layer structure. The method of forming the back panel comprises the step of performing an alloying process. After the alloying process, a pixel mirror layer is formed over the substrate. The pixel mirror layer is electrically connected to the switching device through the interconnect structure. A planar passivation layer is formed on the pixel mirror layer. Then, the planar passivation layer is patterned to expose a portion of the pixel mirror layer.

摘要翻译： 提供了一种用于在基板上制造背板的方法。 基板至少形成有开关装置，并且在其上形成介电层结构。 在电介质层结构中也形成互连结构。 形成后面板的方法包括进行合金化处理的步骤。 在合金化处理之后，在衬底上形成像素镜层。 像素镜层通过互连结构电连接到开关装置。 平面钝化层形成在像素镜面层上。 然后，对平面钝化层进行图案化以暴露像素镜面层的一部分。