公开(公告)号：US08207775B2

公开(公告)日：2012-06-26

申请号：US12871343

申请日：2010-08-30

申请人： Chan-Hong Chern ,  Fu-Lung Hsueh ,  Yuwen Swei ,  Chih-Chang Lin

发明人： Chan-Hong Chern ,  Fu-Lung Hsueh ,  Yuwen Swei ,  Chih-Chang Lin

IPC分类号： H03L5/00

CPC分类号： H03K19/0941 ,  H03K3/356182 ,  H03K19/018514

摘要： A representative level-shifter comprises a dynamically biased current source circuit that receives a first voltage, a first and a second unidirectional current-conducting devices, a first and a second pull-down devices, and a pull-up device. The first and second unidirectional current-conducting devices are coupled to the dynamically biased current source circuit. A voltage output of the level-shifter is located at a first node that is located between the current-constant circuit and the second unidirectional current-conducting device. The first and second pull-down devices are coupled to the first and second unidirectional current-conducting devices, respectively. The pull-up device receives a second voltage and is coupled to the dynamically biased current source circuit and the first unidirectional current-conducting device. The pull-up device is configured to dynamically bias the dynamically biased current source circuit such that a voltage drop of the second unidirectional current-conducting device is output at the voltage output responsive to the pull-up device outputting the second voltage to the dynamically biased current source circuit, the first pull-down device being non-conducting and the second pull-down device being conducting.

摘要翻译： 代表性的电平转换器包括接收第一电压，第一和第二单向导流器件，第一和第二下拉器件以及上拉器件的动态偏置电流源电路。 第一和第二单向导流器件耦合到动态偏置电流源电路。 电平移位器的电压输出位于位于电流恒定电路和第二单向导流器件之间的第一节点处。 第一和第二下拉装置分别耦合到第一和第二单向导流装置。 上拉装置接收第二电压并耦合到动态偏置电流源电路和第一单向导流装置。 上拉装置被配置为动态地偏置动态偏置的电流源电路，使得第二单向导流装置的电压降在电压输出处被输出，响应于上拉装置将第二电压输出到动态偏置 电流源电路，第一下拉装置不导通，第二下拉装置导通。

公开(公告)号：US08193963B2

公开(公告)日：2012-06-05

申请号：US12874462

申请日：2010-09-02

申请人： You-Jen Wang ,  Shen-Iuan Liu ,  Feng-Wei Kuo ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

发明人： You-Jen Wang ,  Shen-Iuan Liu ,  Feng-Wei Kuo ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

IPC分类号： H03M1/50

CPC分类号： G04F10/005

摘要： Methods and apparatuses for time to digital conversion (TDC) are disclosed. A timing circuit comprises a TDC circuit, a calibration module, and a correction module. The TDC circuit is configured to provide a timing signal indicative of a timing difference between edges of a periodic reference clock signal and a variable feedback signal. The TDC circuit is also configured to provide a delay signal that is variably delayed relative to the reference clock signal. The calibration module is configured to provide a calibration signal to increase and decrease a total delay of the TDC circuit based on a time delay of the calibration signal plus a time delay of a correction signal. The correction module, which is configured to receive the timing signal and provide the correction signal, minimizes harmonic spurs in a frequency response of the timing signal by operating at a frequency of the reference clock signal.

摘要翻译： 公开了时间到数字转换（TDC）的方法和装置。 定时电路包括TDC电路，校准模块和校正模块。 TDC电路被配置为提供指示周期性参考时钟信号的边沿与可变反馈信号之间的定时差的定时信号。 TDC电路还被配置为提供相对于参考时钟信号可变地延迟的延迟信号。 校准模块被配置为提供校准信号，以根据校准信号的时间延迟加上校正信号的时间延迟来增加和减少TDC电路的总延迟。 被配置为接收定时信号并提供校正信号的校正模块通过在参考时钟信号的频率下工作来最小化定时信号的频率响应中的谐波杂散。

公开(公告)号：US20120133446A1

公开(公告)日：2012-05-31

申请号：US12957040

申请日：2010-11-30

申请人： Yu-Ling Lin ,  Ying-Ta Lu ,  Hsiao-Tsung Yen ,  Ho-Hsiang Chen ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

发明人： Yu-Ling Lin ,  Ying-Ta Lu ,  Hsiao-Tsung Yen ,  Ho-Hsiang Chen ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

IPC分类号： H03B1/00

CPC分类号： H03B5/1228 ,  H03B5/1215 ,  H03B27/00 ,  H03B2200/0078 ,  H03B2200/0098

摘要： A circuit includes an oscillator circuit including a first oscillator and a second oscillator. The first and the second oscillators are configured to generate signal having a same frequency and different phases. A transmission line is coupled between the first and the second oscillators.

摘要翻译： 电路包括包括第一振荡器和第二振荡器的振荡器电路。 第一和第二振荡器被配置为产生具有相同频率和不同相位的信号。 传输线耦合在第一和第二振荡器之间。

公开(公告)号：US07968971B2

公开(公告)日：2011-06-28

申请号：US12500915

申请日：2009-07-10

申请人： Shine Chung ,  Fu-Lung Hsueh

发明人： Shine Chung ,  Fu-Lung Hsueh

IPC分类号： H01L21/02

CPC分类号： H01L29/7317 ,  H01L29/0692 ,  H01L29/0804

摘要： A thin-body bipolar device includes: a semiconductor substrate, a semiconductor fin constructed over the semiconductor substrate, a first region of the semiconductor fin having a first conductivity type, the first region serving as a base of the thin-body bipolar device, and a second and third region of the semiconductor fin having a second conductivity type opposite to the first conductivity type, the second and third region being both juxtaposed with and separated by the first region, the second and third region serving as an emitter and collector of the thin-body bipolar device, respectively.

摘要翻译： 薄体双极器件包括：半导体衬底，半导体衬底上构造的半导体鳍片，具有第一导电类型的半导体鳍片的第一区域，用作薄体双极器件的基底的第一区域，以及 所述半导体鳍片的第二和第三区域具有与所述第一导电类型相反的第二导电类型，所述第二和第三区域与所述第一区域并置并分隔开，所述第二和第三区域用作所述第一和第三区域的发射极和集电极 薄体双极器件。

公开(公告)号：US07782656B2

公开(公告)日：2010-08-24

申请号：US12178420

申请日：2008-07-23

申请人： Fu-Lung Hsueh ,  Shine Chung ,  Wen-Kuan Fang

发明人： Fu-Lung Hsueh ,  Shine Chung ,  Wen-Kuan Fang

IPC分类号： G11C11/00 ,  G11C5/06 ,  G11C7/10

CPC分类号： G11C11/419 ,  G11C11/412

摘要： A static random access memory (SRAM) cell is disclosed which comprises a cross-couple inverter latch coupled between a positive supply voltage and ground, and having at least a first storage node, and a first and second switching device serially connected between the first storage node and a predetermined voltage source, wherein the first switching device is controlled by a word select signal, and the second switching device is controlled by a first bit select signal, wherein either the word select signal or the first bit select signal is only activated during a write operation.

摘要翻译： 公开了一种静态随机存取存储器（SRAM）单元，其包括耦合在正电源电压和地之间并具有至少第一存储节点的交叉耦合逆变器锁存器，以及串联连接在第一存储器 节点和预定电压源，其中第一开关装置由字选择信号控制，第二开关装置由第一位选择信号控制，其中字选择信号或第一位选择信号仅在 一个写操作。

公开(公告)号：US20100187656A1

公开(公告)日：2010-07-29

申请号：US12618425

申请日：2009-11-13

申请人： Po-Yao Ke ,  Tao-Wen Chung ,  Shine Chung ,  Fu-Lung Hsueh

发明人： Po-Yao Ke ,  Tao-Wen Chung ,  Shine Chung ,  Fu-Lung Hsueh

IPC分类号： H01L29/73

CPC分类号： H01L29/73 ,  H01L21/823431

摘要： Design and methods for fabricating bipolar junction transistors are described. In one embodiment, a semiconductor device includes a first fin comprising a first emitter region, a first base region, and a first collector region. The first emitter region, the first base region, and the first collector region form a bipolar junction transistor. A second fin is disposed adjacent and parallel to the first fin. The second fin includes a first contact to the first base region.

摘要翻译： 描述用于制造双极结型晶体管的设计和方法。 在一个实施例中，半导体器件包括包括第一发射极区域，第一基极区域和第一集电极区域的第一鳍片。 第一发射极区域，第一基极区域和第一集电极区域形成双极结型晶体管。 第二翅片邻近并平行于第一翅片设置。 第二鳍片包括与第一基底区域的第一接触。

公开(公告)号：US20100123483A1

公开(公告)日：2010-05-20

申请号：US12495024

申请日：2009-06-30

申请人： Shine Chung ,  Fu-Lung Hsueh

发明人： Shine Chung ,  Fu-Lung Hsueh

IPC分类号： H03K5/22

CPC分类号： G01R31/3004 ,  G01R31/31703

摘要： A circuit and method for a digital process monitor is disclosed. Circuits for comparing a current or voltage to a current or voltage corresponding to a device having process dependent circuit characteristics are disclosed, having converters for converting current or voltage measurements proportional to the process dependent circuit characteristic to a digital signal and outputting the digital signal for monitoring. The process dependent circuit characteristics may be selected from transistor threshold voltage, transistor saturation current, and temperature dependent quantities. Calibration is performed using digital techniques such as digital filtering and digital signal processing. The digital process monitor circuit may be formed as a scribe line circuit for wafer characterization or placed in an integrated circuit die as a macro. The process monitor circuit may be accessed using probe pads or scan test circuitry. Methods for monitoring process dependent characteristics using digital outputs are disclosed.

摘要翻译： 公开了一种用于数字处理监视器的电路和方法。 公开了用于将电流或电压与对应于具有过程相关电路特性的器件相对应的电流或电压进行比较的电路，具有用于将与过程相关的电路特性成比例的电流或电压测量值转换为数字信号的转换器，并输出用于监测的数字信号 。 处理相关电路特性可以选自晶体管阈值电压，晶体管饱和电流和温度依赖量。 使用数字滤波和数字信号处理等数字技术进行校准。 数字处理监视电路可以形成为用于晶片表征的划线电路或者作为宏放置在集成电路管芯中。 可以使用探针焊盘或扫描测试电路来访问过程监控电路。 公开了使用数字输出来监视与过程有关的特性的方法。

公开(公告)号：US20100020590A1

公开(公告)日：2010-01-28

申请号：US12178420

申请日：2008-07-23

申请人： Fu-Lung Hsueh ,  Shine Chung ,  Wen-Kuan Fang

发明人： Fu-Lung Hsueh ,  Shine Chung ,  Wen-Kuan Fang

IPC分类号： G11C7/00

CPC分类号： G11C11/419 ,  G11C11/412

摘要： A static random access memory (SRAM) cell is disclosed which comprises a cross-couple inverter latch coupled between a positive supply voltage and ground, and having at least a first storage node, and a first and second switching device serially connected between the first storage node and a predetermined voltage source, wherein the first switching device is controlled by a word select signal, and the second switching device is controlled by a first bit select signal, wherein either the word select signal or the first bit select signal is only activated during a write operation.

摘要翻译： 公开了一种静态随机存取存储器（SRAM）单元，其包括耦合在正电源电压和地之间并具有至少第一存储节点的交叉耦合逆变器锁存器，以及串联连接在第一存储器 节点和预定电压源，其中第一开关装置由字选择信号控制，第二开关装置由第一位选择信号控制，其中字选择信号或第一位选择信号仅在 一个写操作。

公开(公告)号：US07633415B2

公开(公告)日：2009-12-15

申请号：US11691872

申请日：2007-03-27

申请人： Shine Chung ,  Fu-Lung Hsueh

发明人： Shine Chung ,  Fu-Lung Hsueh

IPC分类号： H03M1/10

CPC分类号： H03M1/1042 ,  H03M1/687

摘要： A system and method for calibrating a digital-to-analog converter (DAC) is disclosed, the method comprises providing a plurality of spare bits to each of a group of DAC bits that are designated for calibration, calibrating a first DAC bit of the group of DAC bits using its corresponding plurality of spare bits, and keeping a second DAC bit of the group of DAC bits unchanged while calibrating the first DAC bit.

摘要翻译： 公开了一种用于校准数模转换器（DAC）的系统和方法，该方法包括向被指定用于校准的一组DAC位中的每一个提供多个备用位，校准该组的第一DAC位 的DAC位使用其对应的多个备用位，并且在校准第一DAC位的同时保持DAC位组的第二DAC位不变。

公开(公告)号：US07577020B2

公开(公告)日：2009-08-18

申请号：US11865481

申请日：2007-10-01

申请人： Shine Chung ,  Denny Tang ,  Fu-Lung Hsueh

发明人： Shine Chung ,  Denny Tang ,  Fu-Lung Hsueh

IPC分类号： G11C11/00 ,  G11C11/15 ,  G11C15/00

CPC分类号： G11C13/003 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C2213/75 ,  G11C2213/78

摘要： A method for reading two or more magnetic tunnel junctions (MTJs) which are serially connected with a select transistor to form a memory string, the method comprises turning on the select transistor, measuring a first resistance of the memory string, storing the first resistance, toggling a predetermined one of the MTJs, measuring a second resistance of the memory string after the toggling, toggling back the predetermined one of the MTJs and comparing the first and second resistances with a plurality of predetermined resistance values, wherein the comparison result leads to a determination of the data stored in the MTJs.

摘要翻译： 一种用于读取与选择晶体管串联连接以形成存储器串的两个或多个磁隧道结（MTJ）的方法，所述方法包括接通选择晶体管，测量存储器串的第一电阻，存储第一电阻， 切换MTJ中的预定的一个，在切换之后测量存储器串的第二电阻，反转预定的一个MTJ，并用多个预定电阻值比较第一和第二电阻，其中比较结果导致 确定存储在MTJ中的数据。