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    Methods of fabricating field effect transistors having multiple stacked channels
    91.
    发明授权
    Methods of fabricating field effect transistors having multiple stacked channels 有权
    制造具有多个堆叠通道的场效应晶体管的方法

    公开(公告)号：US07381601B2

    公开(公告)日：2008-06-03

    申请号：US10841870

    申请日：2004-05-07

    申请人： Sung-Min Kim ,  Dong-Gun Park ,  Chang-Sub Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Seong-Ho Kim

    发明人： Sung-Min Kim ,  Dong-Gun Park ,  Chang-Sub Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Seong-Ho Kim

    IPC分类号： H01L21/8234 ,  H01L21/336

    CPC分类号： H01L29/785 ,  H01L21/823412 ,  H01L29/42356 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/66787 ,  H01L29/78 ,  H01L29/78642 ,  H01L29/78654 ,  H01L29/78696

    摘要： Integrated circuit field effect transistor devices include a substrate having a surface and an active channel pattern on the surface. The active channel pattern includes channels that are stacked upon one another and are spaced apart from one another to define at least one tunnel between adjacent channels. A gate electrode surrounds the channels and extends through the at least one tunnel. A pair of source/drain regions also is provided. Integrated circuit field effect transistors are manufactured, by forming a pre-active pattern on a surface of a substrate. The pre-active pattern includes a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the substrate at opposite ends of the pre-active pattern. The interchannel layers are selectively removed to form tunnels. A gate electrode is formed in the tunnels and surrounding the channels.

    摘要翻译： 集成电路场效应晶体管器件包括在表面上具有表面和有源沟道图案的衬底。 活动通道图案包括彼此堆叠并且彼此间隔开以限定相邻通道之间的至少一个通道的通道。 栅电极围绕通道并延伸穿过至少一个通道。 还提供了一对源极/漏极区域。 通过在衬底的表面上形成预活性图案来制造集成电路场效应晶体管。 预激活图案包括彼此交替堆叠的一系列通道间层和沟道层。 源极/漏极区域在预活化图案的相对端处在衬底上形成。 选择性地去除通道间层以形成隧道。 在隧道中形成栅电极并围绕通道。

    Transistor and method of forming the same
    98.
    发明授权
    Transistor and method of forming the same 有权
    晶体管及其形成方法

    公开(公告)号：US07919378B2

    公开(公告)日：2011-04-05

    申请号：US12397176

    申请日：2009-03-03

    申请人： Jae-Man Yoon ,  Choong-Ho Lee ,  Dong-Gun Park ,  Chul Lee

    发明人： Jae-Man Yoon ,  Choong-Ho Lee ,  Dong-Gun Park ,  Chul Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L29/785 ,  H01L29/66795

    摘要： According to some embodiments of the invention, a fin type transistor includes an active structure integrally formed with a silicon substrate. The active structure includes grooves that form blocking regions under source/drain regions. A gate structure is formed to cross the upper face of the active structure and to cover the exposed side surfaces of the lateral portions of the active structure. An effective channel length of a fin type transistor may be sufficiently ensured so that a short channel effect of the transistor may be prevented and the fin type transistor may have a high breakdown voltage.

    摘要翻译： 根据本发明的一些实施例，鳍型晶体管包括与硅衬底一体形成的有源结构。 活性结构包括在源极/漏极区域下形成阻挡区的沟槽。 栅极结构形成为跨越有源结构的上表面并且覆盖有源结构的侧部的暴露的侧表面。 可以充分确保翅片型晶体管的有效沟道长度，从而可以防止晶体管的短沟道效应，并且鳍式晶体管可能具有高击穿电压。

    SEMICONDUCTOR DEVICE HAVING VERTICAL TRANSISTOR AND METHOD OF FABRICATING THE SAME
    99.
    发明申请
    SEMICONDUCTOR DEVICE HAVING VERTICAL TRANSISTOR AND METHOD OF FABRICATING THE SAME 有权
    具有垂直晶体管的半导体器件及其制造方法

    公开(公告)号：US20100283094A1

    公开(公告)日：2010-11-11

    申请号：US12840599

    申请日：2010-07-21

    申请人： Bong-Soo Kim ,  Kang-Yoon Lee ,  Dong-Gun Park ,  Jae-Man Yoon ,  Seong-Goo Kim ,  Hyeoung-Won Seo

    发明人： Bong-Soo Kim ,  Kang-Yoon Lee ,  Dong-Gun Park ,  Jae-Man Yoon ,  Seong-Goo Kim ,  Hyeoung-Won Seo

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10894 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7827

    摘要： There are provided a semiconductor device having a vertical transistor and a method of fabricating the same. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. Island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction are formed on the substrate of the cell region. Each of the vertical gate structures includes a semiconductor pillar and a gate electrode surrounding a center portion of the semiconductor pillar. A bit line separation trench is formed inside the semiconductor substrate below a gap region between the vertical gate structures, and a peripheral circuit trench confining a peripheral circuit active region is formed inside the semiconductor substrate of the peripheral circuit region. The bit line separation trench is formed in parallel with the column direction of the vertical gate structures. A bit line separation insulating layer and a peripheral circuit isolation layer are formed inside the bit line separation trench and the peripheral circuit trench, respectively.

    摘要翻译： 提供了具有垂直晶体管的半导体器件及其制造方法。 该方法包括制备具有单元区域和外围电路区域的半导体衬底。 在单元区域的基板上形成沿行方向和列方向二维排列的岛状的垂直栅极结构。 每个垂直栅极结构包括半导体柱和围绕半导体柱的中心部分的栅电极。 在垂直栅极结构之间的间隙区域的下方，在半导体衬底的内部形成有位线分离沟槽，并且在外围电路区域的半导体衬底的内部形成限制外围电路有源区的外围电路沟道。 位线分离沟槽与垂直栅极结构的列方向平行地形成。 位线分离绝缘层和外围电路隔离层分别形成在位线分离沟槽和外围电路沟槽内部。

    Method of forming fin field effect transistor using damascene process
    100.
    发明授权
    Method of forming fin field effect transistor using damascene process 有权
    使用镶嵌工艺形成翅片场效应晶体管的方法

    公开(公告)号：US07528022B2

    公开(公告)日：2009-05-05

    申请号：US11112818

    申请日：2005-04-21

    申请人： Young-Joon Ahn ,  Dong-Gun Park ,  Choong-Ho Lee ,  Hee-Soo Kang

    发明人： Young-Joon Ahn ,  Dong-Gun Park ,  Choong-Ho Lee ,  Hee-Soo Kang

    IPC分类号： H01L21/8234

    CPC分类号： H01L29/7851 ,  H01L21/26586 ,  H01L29/66818

    摘要： A method of forming a fin transistor using a damascene process is provided. A filling mold insulation pattern is recessed to expose an upper portion of a fin, and a mold layer is formed. The mold layer is patterned to form a groove crossing the fin and exposing a part of the upper portion of the fin. A gate electrode is formed to fill the groove with a gate insulation layer interposed between the fin and the gate electrode, and the mold layer is removed. Impurities are implanted through both sidewalls and a top surface of the upper portion of the fin disposed at opposite sides of a gate electrode to form a source/drain region.

    摘要翻译： 提供了一种使用镶嵌工艺形成鳍式晶体管的方法。 填充模具绝缘图案凹入以暴露翅片的上部，并且形成模具层。 图案化模具层以形成与散热片交叉的凹槽并暴露翅片上部的一部分。 形成栅电极，用插入翅片和栅电极之间的栅极绝缘层填充凹槽，并且去除模层。 通过设置在栅极电极的相对侧的翅片的上侧部分的两个侧壁和顶部表面注入杂质以形成源极/漏极区域。