公开(公告)号：US11203522B2

公开(公告)日：2021-12-21

申请号：US16990092

申请日：2020-08-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wei Lin ,  Chang-Ming Wu ,  Ting-Jung Chen

IPC: B81B3/00 ,  B81B1/00 ,  B81C1/00

Abstract: The present disclosure relates to a microphone. In some embodiments, the microphone may comprise a diaphragm, a backplate, and a sidewall stopper. The diaphragm has a venting hole disposed therethrough. The backplate is disposed over and spaced apart from the diaphragm. The sidewall stopper is disposed along a sidewall of the diaphragm exposing to the venting hole. Thus, the sidewall stopper is not limited by a distance between the movable part and the stable part of the microphone. Also, the sidewall stopper does not alternate the shape of movable part, and thus will less likely introduce crack to the movable part. In some embodiments, the sidewall stopper may be formed like a sidewall stopper by a self-alignment process, such that no extra mask is needed.

公开(公告)号：US20200369512A1

公开(公告)日：2020-11-26

申请号：US16990106

申请日：2020-08-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wei Lin ,  Chang-Ming Wu ,  Ting-Jung Chen

IPC: B81B3/00 ,  B81B1/00 ,  B81C1/00

Abstract: The present disclosure relates to a method of manufacturing a MEMS device. In some embodiments, a first interlayer dielectric layer is formed over a substrate, and a diaphragm is formed over the first interlayer dielectric layer. Then, a second interlayer dielectric layer is formed over the diaphragm. A first etch is performed to form an opening through the second interlayer dielectric layer and the diaphragm and reaching into an upper portion of the first interlayer dielectric layer. A second etch is performed to the first interlayer dielectric layer and the second interlayer dielectric layer to form recesses above and below the diaphragm and to respectively expose a portion of a top surface and a portion of a bottom surface of the diaphragm. A sidewall stopper is formed along a sidewall of the diaphragm into the recesses of the first interlayer dielectric layer and the second interlayer dielectric layer.

公开(公告)号：US20200369511A1

公开(公告)日：2020-11-26

申请号：US16990092

申请日：2020-08-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wei Lin ,  Chang-Ming Wu ,  Ting-Jung Chen

IPC: B81B3/00 ,  B81B1/00 ,  B81C1/00

Abstract: The present disclosure relates to a microphone. In some embodiments, the microphone may comprise a diaphragm, a backplate, and a sidewall stopper. The diaphragm has a venting hole disposed therethrough. The backplate is disposed over and spaced apart from the diaphragm. The sidewall stopper is disposed along a sidewall of the diaphragm exposing to the venting hole. Thus, the sidewall stopper is not limited by a distance between the movable part and the stable part of the microphone. Also, the sidewall stopper does not alternate the shape of movable part, and thus will less likely introduce crack to the movable part. In some embodiments, the sidewall stopper may be formed like a sidewall stopper by a self-alignment process, such that no extra mask is needed.

公开(公告)号：US20200266205A1

公开(公告)日：2020-08-20

申请号：US16869780

申请日：2020-05-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Wei Cheng Wu ,  Shih-Chang Liu ,  Harry-Hak-Lay Chuang ,  Chia-Shiung Tsai

IPC: H01L27/11568 ,  H01L29/792 ,  H01L29/423 ,  H01L21/311 ,  H01L29/66

Abstract: A device comprises a control gate structure and a memory gate structure over a substrate, a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer along a sidewall of the control gate structure, an oxide layer over a top surface of the memory gate structure, a top spacer over the oxide layer, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.

公开(公告)号：US20190097009A1

公开(公告)日：2019-03-28

申请号：US16166603

申请日：2018-10-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Wei Cheng Wu ,  Shih-Chang Liu ,  Harry-Hak-Lay Chuang ,  Chia-Shiung Tsai

IPC: H01L29/423 ,  H01L27/11568 ,  H01L27/1157 ,  H01L29/792 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L27/11521

Abstract: The present disclosure, in some embodiments, relates to a method of forming a memory cell. The method may be performed by forming a select gate on a side of a sacrificial spacer that is disposed over an upper surface of a substrate. The select gate has a non-planar top surface. An inter-gate dielectric layer is formed on the select gate and a memory gate is formed on the inter-gate dielectric layer. The inter-gate dielectric layer extends under the memory gate and defines a recess between sidewalls of the memory gate and select gate. The recess is filled with a first dielectric material.

公开(公告)号：US20190094682A1

公开(公告)日：2019-03-28

申请号：US16013163

申请日：2018-06-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ping-Yin Liu ,  Chang-Ming Wu ,  Chia-Shiung Tsai ,  Xin-Hua Huang

IPC: G03F1/64 ,  G03F7/20

CPC classification number: G03F1/64 ,  G03F1/62 ,  G03F7/7015

Abstract: A method for forming a pellicle apparatus involves forming a device substrate by depositing one or more pellicle layers defined over a base device layer, where a release layer is formed thereover. An adhesive layer is formed over a transparent carrier substrate. The adhesive layer is bonded to the release layer, defining a composite substrate comprised of the device and carrier substrates. The base device layer is removed from the composite structure and a pellicle frame is attached to an outermost one of the pellicle layers. A pellicle region is isolated from a remainder of the composite structure, and an ablation of the release layer is performed through the transparent carrier substrate, defining the pellicle apparatus comprising a pellicle film attached to the pellicle frame. The pellicle apparatus is then from a remaining portion of the composite substrate.

公开(公告)号：US09716097B2

公开(公告)日：2017-07-25

申请号：US14596340

申请日：2015-01-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Shih-Chang Liu ,  Sheng-Chieh Chen ,  Yung-Chang Chang

IPC: H01L27/115 ,  H01L27/11521 ,  H01L29/423 ,  H01L21/265 ,  H01L21/3213 ,  H01L21/311 ,  H01L29/788 ,  H01L27/11534

CPC classification number: H01L27/11521 ,  H01L21/26513 ,  H01L21/31116 ,  H01L21/32137 ,  H01L21/32139 ,  H01L27/11534 ,  H01L29/42328 ,  H01L29/7881 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments of the present disclosure relate to a flash memory device. The flash memory device includes first and second individual source/drain (S/D) regions spaced apart within a semiconductor substrate. A common S/D region is arranged laterally between the first and second individual S/D regions, and is separated from the first individual S/D region by a first channel region and is separated from the second individual S/D region by a second channel region. An erase gate is arranged over the common S/D. A floating gate is disposed over the first channel region and is arranged to a first side of the erase gate. A control gate is disposed over the floating gate. A wordline is disposed over the first channel region and is spaced apart from the erase gate by the floating gate and the control gate. An upper surface of the wordline is a concave surface.

公开(公告)号：US09711508B2

公开(公告)日：2017-07-18

申请号：US14632569

申请日：2015-02-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tsung-Hsueh Yang ,  Chung-Chiang Min ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L27/108 ,  H01L49/02

CPC classification number: H01L27/10808 ,  H01L27/10852 ,  H01L28/90

Abstract: A capacitor structure includes a deep trench, a contact plug, a spacer and a metal-insulator-metal film. The deep trench extends into a crown oxide substrate, and the contact plug is disposed entirely below the crown oxide substrate. The spacer lines the deep trench, and the metal-insulator-metal film is disposed in the deep trench.

公开(公告)号：US09691883B2

公开(公告)日：2017-06-27

申请号：US14308872

申请日：2014-06-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chieh Chen ,  Yuan-Tai Tseng ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L29/788 ,  H01L29/66 ,  H01L29/49 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/4983 ,  H01L29/6656 ,  H01L29/7883

Abstract: A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate having a source region and a drain region. Further, the semiconductor structure includes a floating gate, a word line, and an erase gate spaced over the semiconductor substrate between the source and drain regions with the floating gate arranged between the word line and the erase gate. The semiconductor structure further includes a first dielectric sidewall region disposed between the word line and the floating gate, as well as a second dielectric sidewall region disposed between the erase and floating gates. A thickness of the first dielectric sidewall region is greater than a thickness of the second dielectric sidewall region. A method of manufacturing the semiconductor structure and an integrated circuit including the semiconductor structure are also provided.

公开(公告)号：US09646978B2

公开(公告)日：2017-05-09

申请号：US14729553

申请日：2015-06-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/423 ,  H01L23/528 ,  H01L21/768 ,  H01L29/788 ,  H01L29/78

CPC classification number: H01L27/11519 ,  H01L21/28273 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76883 ,  H01L23/5283 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7831 ,  H01L29/788 ,  H01L29/7881

Abstract: The present disclosure relates to a flash memory device, and associated methods. In some embodiments, the flash memory device has a gate stack with a control gate separated from a floating gate by a control gate dielectric. An erase gate disposed on a first side of the gate stack. A word line is disposed on a second side of the gate stack that is opposite the first side. The word line has a height that monotonically increases from an outer side opposite to the gate stack to an inner side closer to the gate stack. The shape of the word line optimizes the contact resistance of the word line and allows for an overlying cap spacer formed on the word line to be well defined, which can provide more reliable read/write operations and/or better performance.