公开(公告)号：US09728521B2

公开(公告)日：2017-08-08

申请号：US14806888

申请日：2015-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Cheng Tsai ,  Chun-Chieh Chuang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Chih-Hui Huang ,  Yan-Chih Lu ,  Ju-Shi Chen

IPC: H01L25/065 ,  H01L23/528 ,  H01L23/532 ,  H01L25/00 ,  H01L23/00 ,  H01L23/522 ,  H01L21/768 ,  H01L21/321 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L25/0657 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31111 ,  H01L21/3212 ,  H01L21/76807 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L24/80 ,  H01L24/89 ,  H01L25/50 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/08145 ,  H01L2224/215 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/94 ,  H01L2225/06524 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/0104 ,  H01L2924/01072 ,  H01L2224/80

Abstract: An integrated circuit (IC) using a copper-alloy based hybrid bond is provided. The IC comprises a pair of semiconductor structures vertically stacked upon one another. The pair of semiconductor structures comprise corresponding dielectric layers and corresponding metal features arranged in the dielectric layers. The metal features comprise a copper alloy having copper and a secondary metal. The IC further comprises a hybrid bond arranged at an interface between the semiconductor structures. The hybrid bond comprises a first bond bonding the dielectric layers together and a second bond bonding the metal features together. The second bond comprises voids arranged between copper grains of the metal features and filled by the secondary metal. A method for bonding a pair of semiconductor structures together using the copper-alloy based hybrid bond is also provided.

公开(公告)号：US20170186798A1

公开(公告)日：2017-06-29

申请号：US14980386

申请日：2015-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hsien Yang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Feng-Chi Hung ,  Shyh-Fann Ting ,  Chun-Yuan Chen

IPC: H01L27/146 ,  H01L31/107

CPC classification number: H01L27/14634 ,  H01L27/14612 ,  H01L27/1462 ,  H01L27/14629 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14687 ,  H01L27/1469 ,  H01L31/03529 ,  H01L31/107

Abstract: The present disclosure relates to a stacked SPAD image sensor with a CMOS Chip and an imaging chip bonded together, to improve the fill factor of the SPAD image sensor, and an associated method of formation. In some embodiments, the imaging chip has a plurality of SPAD cells disposed within a second substrate. The CMOS Chip has a first interconnect structure disposed over a first substrate. The imaging chip has a second interconnect structure disposed between the second substrate and the first interconnect structure. The CMOS Chip and the imaging chip are bonded together through along an interface disposed between the first interconnect structure and the second interconnect structure.

公开(公告)号：US20170133414A1

公开(公告)日：2017-05-11

申请号：US14935819

申请日：2015-11-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chiang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsiao-Hui Tseng ,  Chih-Hui Huang ,  Shyh-Fann Ting ,  Shih Pei Chou ,  Sheng-Chan Li

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14685 ,  H01L27/14689

Abstract: The present disclosure relates to a BSI image sensor with improved DTI structures, and an associated method of formation. In some embodiments, the BSI image sensor comprises a plurality of image sensing elements disposed within a substrate corresponding to a plurality of pixel regions. A deep trench isolation (DTI) grid is disposed between adjacent image sensing elements and extending from an upper surface of the substrate to positions within the substrate. The DTI grid comprises air-gaps disposed under the upper surface of the substrate, the air-gaps having lower portions surrounded by a first dielectric layer and some upper portions sealed by a second dielectric layer.

公开(公告)号：US20170117309A1

公开(公告)日：2017-04-27

申请号：US14923635

申请日：2015-10-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsiao-Hui Tseng ,  Jhy-Jyi Sze ,  Shyh-Fann Ting ,  Tzu-Jui Wang ,  Yen-Ting Chiang ,  Yu-Jen Wang ,  Yuichiro Yamashita

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14609 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14689

Abstract: The present disclosure relates to a CMOS image sensor having a doped region, arranged between deep trench isolation structures and an image sensing element, and an associated method of formation. In some embodiments, the CMOS image sensor has a pixel region disposed within a semiconductor substrate. The pixel region has an image sensing element configured to convert radiation into an electric signal. A plurality of back-side deep trench isolation (BDTI) structures extend into the semiconductor substrate on opposing sides of the pixel region. A doped region is laterally arranged between the BDTI structures and separates the image sensing element from the BDTI structures and the back-side of the semiconductor substrate. Separating the image sensing element from the BDTI structures prevents the image sensing element from interacting with interface defects near edges of the BDTI structures, and thereby reduces dark current and white pixel number.