利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

184 条记录 (耗时 0.036 秒)

    Adjustable Dummy Fill
    91.
    发明申请
    Adjustable Dummy Fill 有权
    可调节虚拟填充

    公开(公告)号：US20110004859A1

    公开(公告)日：2011-01-06

    申请号：US12883741

    申请日：2010-09-16

    申请人： Scott R. Summerfelt ,  Robert G. Fleck

    发明人： Scott R. Summerfelt ,  Robert G. Fleck

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072 ,  G06F17/5068 ,  G06F2217/12 ,  H01L22/26 ,  H01L27/0207 ,  H01L27/11507 ,  Y02P90/265

    摘要： A method of placing a dummy fill layer on a substrate is disclosed (FIG. 2). The method includes identifying a sub-region of the substrate (210). A density of a layer in the sub-region is determined (212). A pattern of the dummy fill layer is selected to produce a predetermined density (216). The selected pattern is placed in the sub-region (208).

    摘要翻译： 公开了一种在衬底上放置虚拟填充层的方法（图2）。 该方法包括识别衬底（210）的子区域。 确定子区域中的层的密度（212）。 选择虚拟填充层的图案以产生预定的密度（216）。 所选择的图案被放置在子区域（208）中。

    Modeling of Ferroelectric Capacitors to Include Local Statistical Variations of Ferroelectric Properties
    92.
    发明申请
    Modeling of Ferroelectric Capacitors to Include Local Statistical Variations of Ferroelectric Properties 有权
    铁电电容的建模包括铁电性质的局部统计变化

    公开(公告)号：US20100299115A1

    公开(公告)日：2010-11-25

    申请号：US12568910

    申请日：2009-09-29

    申请人： Borna Obradovic ,  Keith R. Green ,  Scott R. Summerfelt

    发明人： Borna Obradovic ,  Keith R. Green ,  Scott R. Summerfelt

    IPC分类号： G06F17/10

    CPC分类号： G06F17/5036

    摘要： Simulation of an electronic circuit including a model of a ferroelectric capacitor. The model of the ferroelectric capacitor includes a multi-domain ferroelectric capacitor, in which each of the domains is associated with a positive and a negative coercive voltage. A probability distribution function of positive and negative coercive voltages is defined, from which a weighting function of the distribution of domains having those coercive voltages is defined. To create a model of a small ferroelectric capacitor, a Poisson probability distribution is assigned to each of an array of gridcells defining the probability distribution function of positive and negative coercive voltages, and a number of domains assigned to each gridcell is randomly selected according to that Poisson distribution and an expected number of domains in the modeled capacitor for that gridcell, based on the area of the modeled capacitor. The electrical behavior of the ferroelectric capacitor is evaluated by evaluating the superposed polarization of each of the randomly selected domains.

    摘要翻译： 包括铁电电容器型号的电子电路仿真。 铁电电容器的模型包括多畴铁电电容器，其中每个畴与正矫顽电压和负矫顽电压相关联。 定义正矫顽电压和负矫顽电压的概率分布函数，从而确定具有矫顽电压的域的分布的加权函数。 为了创建小型铁电电容器的模型，将Poisson概率分布分配给定义正和负矫顽电压的概率分布函数的网格单元阵列中的每一个，并且分配给每个网格单元的域的数量根据该格子随机选择 基于建模电容器的面积，该网格单元的建模电容器的泊松分布和预期数量的域。 通过评估每个随机选择的畴的叠加极化来评估铁电电容器的电性能。

    Enhanced local interconnects employing ferroelectric electrodes
    93.
    发明申请
    Enhanced local interconnects employing ferroelectric electrodes 有权
    使用铁电电极的增强型局部互连

    公开(公告)号：US20080121953A1

    公开(公告)日：2008-05-29

    申请号：US11519313

    申请日：2006-09-12

    申请人： Scott R. Summerfelt

    发明人： Scott R. Summerfelt

    IPC分类号： H01L27/115 ,  H01L21/8246

    CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/65

    摘要： A ferroelectric device employs ferroelectric electrodes as local interconnect(s). One or more circuit features are formed within or on a semiconductor body. A first dielectric layer is formed over the semiconductor body. Lower contacts are formed within the first dielectric layer. A bottom electrode is formed over the first dielectric layer and on the lower contacts. A ferroelectric layer is formed on the bottom electrode. A top electrode is formed on the ferroelectric layer. A second dielectric layer is formed over the first dielectric layer. Upper contacts are formed within the second dielectric layer and in contact with the top electrode. Conductive features are formed on the upper contacts.

    摘要翻译： 铁电体采用铁电电极作为局部互连。 一个或多个电路特征形成在半导体本体内或上。 第一介电层形成在半导体本体上。 在第一电介质层内形成下触点。 底部电极形成在第一电介质层上和下触点上。 在底部电极上形成铁电体层。 在铁电层上形成顶部电极。 在第一电介质层上形成第二电介质层。 上部触点形成在第二电介质层内并与顶部电极接触。 导电特征形成在上触点上。

    PZT (111) texture through Ir texture improvement
    96.
    发明授权
    PZT (111) texture through Ir texture improvement 有权
    PZT（111）纹理通过Ir纹理改进

    公开(公告)号：US06872669B1

    公开(公告)日：2005-03-29

    申请号：US10742190

    申请日：2003-12-19

    申请人： Scott R. Summerfelt ,  Sanjeev Aggarwal

    发明人： Scott R. Summerfelt ,  Sanjeev Aggarwal

    IPC分类号： H01L21/02 ,  H01L21/302 ,  H01L21/314 ,  H01L21/316 ,  H01L21/321 ,  H01L21/3213

    CPC分类号： H01L28/55 ,  H01L21/3145 ,  H01L21/31691 ,  H01L21/3212 ,  H01L21/32131 ,  H01L28/65 ,  H01L28/75

    摘要： The present invention is directed to a method of forming a ferroelectric capacitor having a (111) PZT texture. The method includes forming a smooth bottom electrode diffusion barrier layer that facilitates a preferential (111) texture in the subsequently formed bottom electrode layer. The (111) bottom electrode layer texture than facilitates a high quality (111) texture in the overlying PZT layer, thereby improving bit-to-bit polarization charge uniformity for various capacitors as the ferroelectric capacitor sizes continue to shrink.

    摘要翻译： 本发明涉及形成具有（111）PZT纹理的铁电电容器的方法。 该方法包括形成平滑的底部电极扩散阻挡层，其有利于随后形成的底部电极层中的优先（111）纹理。 （111）底电极层结构有利于上覆PZT层中的高质量（111）纹理，从而提高了随着铁电电容器尺寸的不断缩小，各种电容器的位对齐极化电荷均匀性。

    VIA0 etch process for FRAM integration
    97.
    发明授权
    VIA0 etch process for FRAM integration 有权
    用于FRAM集成的VIA0蚀刻工艺

    公开(公告)号：US06841396B2

    公开(公告)日：2005-01-11

    申请号：US10440697

    申请日：2003-05-19

    申请人： Francis Gabriel Celii ,  K. R. Udayakumar ,  Scott R. Summerfelt ,  Theodore S. Moise

    发明人： Francis Gabriel Celii ,  K. R. Udayakumar ,  Scott R. Summerfelt ,  Theodore S. Moise

    IPC分类号： H01L21/00 ,  H01L21/20 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/115

    CPC分类号： H01L27/11502 ,  H01L27/11507

    摘要： A ferroelectric memory device comprises a logic programmable capacitance reference circuit. The circuit is adapted to generate a reference voltage during a sense mode of operation, wherein the reference voltage comprises a value that is a function of one more memory conditions. The memory device further comprises a bit line pair, wherein a first bit line of the bit line pair has a ferroelectric capacitor coupled thereof for sensing thereof, and a second bit line of the bit line pair is coupled to the reference voltage. A sense circuit is coupled to the bit line pair and is configured to detect a data state associated with the ferroelectric capacitor using a voltage associated with the first bit line and reference voltage on the second bit line.

    摘要翻译： 铁电存储器件包括逻辑可编程电容参考电路。 电路适于在感测操作模式期间产生参考电压，其中参考电压包括作为一个以上存储器条件的函数的值。 存储器件还包括位线对，其中位线对的第一位线具有耦合的铁电电容器用于感测位线对，并且位线对的第二位线耦合到参考电压。 感测电路耦合到位线对，并且被配置为使用与第一位线相关联的电压和第二位线上的参考电压来检测与铁电电容器相关联的数据状态。

    Method of fabricating a ferroelectric memory cell
    99.
    发明授权
    Method of fabricating a ferroelectric memory cell 有权
    制造铁电存储单元的方法

    公开(公告)号：US06548343B1

    公开(公告)日：2003-04-15

    申请号：US09702985

    申请日：2000-10-31

    申请人： Scott R. Summerfelt ,  Theodore S. Moise ,  Guoqiang Xing ,  Luigi Colombo ,  Tomoyuki Sakoda ,  Stephen R. Gilbert ,  Alvin L. S. Loke ,  Shawming Ma ,  Rahim Kavari ,  Laura Wills-Mirkarimi ,  Jun Amano

    发明人： Scott R. Summerfelt ,  Theodore S. Moise ,  Guoqiang Xing ,  Luigi Colombo ,  Tomoyuki Sakoda ,  Stephen R. Gilbert ,  Alvin L. S. Loke ,  Shawming Ma ,  Rahim Kavari ,  Laura Wills-Mirkarimi ,  Jun Amano

    IPC分类号： H01L218242

    CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/57

    摘要： An embodiment of the instant invention is a method of fabricating a ferroelectric capacitor which is situated over a structure, the method comprising the steps of: forming a bottom electrode on the structure (124 of FIG. 1), the bottom electrode having a top surface and sides; forming a capacitor dielectric (126 of FIG. 1) comprised of a ferroelectric material on the bottom electrode, the capacitor dielectric having a top surface and sides; forming a top electrode (128 and 130 of FIG. 1) on the capacitor dielectric, the top electrode having a top surface and sides, the ferroelectric capacitor is comprised of the bottom electrode, the capacitor dielectric, and the top electrode; forming a barrier layer (118 and 120 of FIG. 1) on the side of the bottom electrode, the side of the capacitor dielectric, and the side of the top electrode; forming a dielectric layer on the barrier layer and the structure, the dielectric having a top surface and a bottom surface; and performing a thermal step for a duration at a temperature between 400 and 900 C. in an ambient comprised of a gas selected from the group consisting of: argon, nitrogen, and a combination thereof, the step of performing a thermal step being performed after the step of forming the barrier layer.

    摘要翻译： 本发明的一个实施例是制造位于结构上方的铁电电容器的方法，所述方法包括以下步骤：在所述结构（图1的124）上形成底电极，所述底电极具有顶表面 和边; 在底部电极上形成由铁电材料构成的电容器电介质（图1的126），电容器电介质具有顶表面和侧面; 在电容器电介质上形成顶电极（图1的128和130），顶电极具有顶表面和侧面，铁电电容器由底电极，电容器电介质和顶电极组成; 在底电极侧，电容器电介质侧和顶电极侧形成阻挡层（图1的118和120）; 在所述阻挡层和所述结构上形成电介质层，所述电介质具有顶表面和底表面; 并且在由选自氩，氮及其组合的气体组成的环境中在400-900℃的温度下进行热步骤，所述环境包括：在步骤 形成阻挡层的步骤。