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公开(公告)号：US20090079030A1
公开(公告)日：2009-03-26
申请号：US12169727
申请日：2008-07-09
CPC分类号： H01L27/10867 , H01L27/0207
摘要： A method of forming a trench memory cell includes forming a trench capacitor within a substrate material, the trench capacitor including a node dielectric layer formed within a trench and a conductive capacitor electrode material formed within the trench in contact with the node dielectric layer; forming a strap mask so as cover one side of the trench and removing one or more materials from an uncovered opposite side of the trench; and forming a conductive buried strap material within the trench; wherein the strap mask is patterned in a manner such that a single-sided buried strap is defined within the trench, the single-sided buried strap configured in a manner such that the deep trench capacitor is electrically accessible at only one side of the trench.
摘要翻译： 形成沟槽存储单元的方法包括在衬底材料内形成沟槽电容器，所述沟槽电容器包括形成在沟槽内的节点电介质层和形成在所述沟槽内与所述节点电介质层接触的导电电容器电极材料; 形成带状掩模，以覆盖沟槽的一侧，并从沟槽的未覆盖的相对侧移除一种或多种材料; 以及在所述沟槽内形成导电掩埋带材料; 其中所述带掩模被图案化，使得在所述沟槽内限定单面掩埋带，所述单侧埋入带以使得所述深沟槽电容器仅在所述沟槽的一侧电可访问的方式构造。
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92.发明申请SIMULTANEOUSLY FORMING HIGH-SPEED AND LOW-POWER MEMORY DEVICES ON A SINGLE SUBSTRATE 审中-公开同时在单个基板上同时形成高速和低功耗存储器件公开(公告)号：US20080160713A1
公开(公告)日：2008-07-03
申请号：US11617960
申请日：2006-12-29
IPC分类号： H01L21/28
CPC分类号： H01L27/1203 , H01L27/0733 , H01L27/1207 , H01L29/945
摘要： A method patterns a trench mask over both SOI regions and bulk silicon regions of a single substrate. Next, the SOI regions and the bulk silicon regions are simultaneously etched through the trench mask to form trenches in the SOI regions and the bulk silicon regions. In such processing the buried insulating layer in SOI regions causes trenches within the SOI regions to be less deep (more shallow) than trenches in the bulk silicon regions (which are deeper or less shallow). After the trenches are formed, the method completes the process by forming capacitors in the trenches. More specifically, the method simultaneously lines all of the trenches with an insulator and simultaneously fills all of the trenches with a conductor to form capacitors in the trenches. The capacitors within the SOI regions have a lower capacitance that the capacitors within the SOI regions.
摘要翻译： 一种方法在单个衬底的SOI区域和体硅区域上形成沟槽掩模。 接下来，通过沟槽掩模同时蚀刻SOI区域和体硅区域，以在SOI区域和体硅区域中形成沟槽。 在这种处理中，SOI区域中的掩埋绝缘层使得SOI区域内的沟槽比体硅区域（更深或更浅）中的沟槽更深（更浅）。 在沟槽形成之后，该方法通过在沟槽中形成电容器来完成该工艺。 更具体地，该方法同时用绝缘体对所有沟槽进行排列，同时用导体填充所有沟槽，以在沟槽中形成电容器。 SOI区域内的电容器具有较低的电容，即SOI区域内的电容器。
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93.发明申请公开(公告)号：US20070284640A1
公开(公告)日：2007-12-13
申请号：US11423284
申请日：2006-06-09
IPC分类号： H01L29/94
CPC分类号： H01L29/945 , H01L29/66931
摘要： A semiconductor structure and a method for forming the same. The semiconductor structure includes a semiconductor substrate. The semiconductor structure further includes an electrically insulating region on top of the semiconductor substrate. The semiconductor structure further includes a first semiconductor region on top of and in direct physical contact with the semiconductor substrate. The semiconductor structure further includes a second semiconductor region on top of the insulating region. The semiconductor structure further includes a capacitor in the first semiconductor region and the semiconductor substrate. The semiconductor structure further includes a capacitor electrode contact in the second semiconductor region and the electrically insulating region.
摘要翻译： 半导体结构及其形成方法。 半导体结构包括半导体衬底。 半导体结构还包括在半导体衬底的顶部上的电绝缘区域。 半导体结构还包括在半导体衬底之上并与之直接物理接触的第一半导体区域。 半导体结构还包括在绝缘区域的顶部上的第二半导体区域。 半导体结构还包括在第一半导体区域和半导体衬底中的电容器。 半导体结构还包括在第二半导体区域和电绝缘区域中的电容器电极接触。
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94.发明申请SELF-ALIGNED BODY CONTACT FOR A SEMICONDCUTOR-ON-INSULATOR TRENCH DEVICE AND METHOD OF FABRICATING SAME 有权用于半导体绝缘体固化器的自对准身体接触件及其制造方法公开(公告)号：US20070235801A1
公开(公告)日：2007-10-11
申请号：US11308542
申请日：2006-04-04
IPC分类号： H01L29/94
CPC分类号： H01L29/7827 , H01L21/84 , H01L27/0207 , H01L27/10841 , H01L27/10876 , H01L29/66666 , H01L2924/0002 , H01L2924/00
摘要： A structure and method of forming a body contact for an semiconductor-on-insulator trench device. The method including: forming set of mandrels on a top surface of a substrate, each mandrel of the set of mandrels arranged on a different corner of a polygon and extending above the top surface of the substrate, a number of mandrels in the set of mandrels equal to a number of corners of the polygon; forming sidewall spacers on sidewalls of each mandrel of the set of mandrels, sidewalls spacers of each adjacent pair of mandrels merging with each other and forming a unbroken wall defining an opening in an interior region of the polygon, a region of the substrate exposed in the opening; etching a contact trench in the substrate in the opening; and filling the contact trench with an electrically conductive material to form the contact.
摘要翻译： 一种用于形成绝缘体上半导体沟槽器件的体接触的结构和方法。 该方法包括：在基板的顶表面上形成一组心轴，该组心轴的每个心轴布置在多边形的不同角上并且在衬底的顶表面上方延伸，该心轴组中的多个心轴 等于多边形的多个角; 在所述一组心轴的每个心轴的侧壁上形成侧壁间隔件，每个相邻的一对心轴的侧壁间隔件彼此合并并且形成在多边形的内部区域中限定开口的不间断的壁， 开口 蚀刻开口中的衬底中的接触沟槽; 以及用导电材料填充接触沟槽以形成接触。
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公开(公告)号：US20070222015A1
公开(公告)日：2007-09-27
申请号：US11750423
申请日：2007-05-18
IPC分类号： H01L31/0352
CPC分类号： H01L31/105 , H01L31/03529 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： Trench type PIN photodetectors are formed by etching two sets of trenches simultaneously in a semiconductor substrate, the wide trenches having a width more than twice as great as the narrow trenches by a process margin; conformally filling both types of trenches with a sacrificial material doped with a first dopant and having a first thickness slightly greater than one half the width of the narrow trenches, so that the wide trenches have a remaining central aperture; stripping the sacrificial material from the wide trenches in an etch that removes a first thickness, thereby emptying the wide trenches; a) filling the wide trenches with a second sacrificial material of opposite polarity; or b) doping the wide trenches from the ambient such as by gas phase doping, plasma doping, ion implantation, liquid phase doping, infusion doping and plasma immersion ion implantation; diffusing the dopants into the substrate, forming p and n regions of the PIN diode; removing the first and the second sacrificial materials, and filling both the wide and the narrow sets of trenches with the same conductive material in contact with the diffused p and n regions.
摘要翻译： 通过在半导体衬底中同时蚀刻两组沟槽形成沟槽型PIN光电检测器，宽沟槽的宽度是窄沟槽的两倍以上的加工余量; 用掺杂有第一掺杂剂的牺牲材料保形地填充两种类型的沟槽，并且具有略大于窄沟槽宽度的一半的第一厚度，使得宽沟槽具有剩余的中心孔径; 在去除第一厚度的蚀刻中从宽的沟槽剥离牺牲材料，从而排空宽的沟槽; a）用相反极性的第二牺牲材料填充宽的沟槽; 或b）通过气相掺杂，等离子体掺杂，离子注入，液相掺杂，浸渍掺杂和等离子体浸入离子注入等方式，从环境中掺杂宽沟槽; 将掺杂剂扩散到衬底中，形成PIN二极管的p区和n区; 去除第一和第二牺牲材料，并用与扩散的p和n区域接触的相同导电材料填充宽和窄的沟槽组。
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公开(公告)号：US07211474B2
公开(公告)日：2007-05-01
申请号：US10905708
申请日：2005-01-18
IPC分类号： H01L21/84
CPC分类号： H01L21/76205 , H01L21/76235 , H01L21/823412 , H01L21/823481
摘要： A region of a semiconductor wafer is converted to an SOI structure by etching a set of isolation trenches for each transistor active area and oxidizing the sidewalls of the trenches to a depth that leaves a pillar of semiconductor that forms a body contact extending from the active area downward to the bulk semiconductor. A self-aligned gate is then formed above the body contact.
摘要翻译： 半导体晶片的区域通过蚀刻用于每个晶体管有源区的一组隔离沟槽并将沟槽的侧壁氧化成离开形成从有源区域延伸的主体接触的半导体柱的深度而被转换为SOI结构 向下到散装半导体。 然后在身体接触物上方形成自对准门。
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公开(公告)号：US20060292789A1
公开(公告)日：2006-12-28
申请号：US11468543
申请日：2006-08-30
IPC分类号： H01L21/8242 , H01L29/94
CPC分类号： H01L21/3081 , H01L27/10864 , H01L27/10867 , H01L27/1087
摘要： A structure and method are provided for forming a collar surrounding a portion of a trench in a semiconductor substrate, the collar having a lower edge self-aligned to a top edge of a buried plate disposed adjacent to a lower portion of the trench.
摘要翻译： 提供一种用于形成围绕半导体衬底中的沟槽的一部分的环的结构和方法，所述套环具有与邻近所述沟槽的下部设置的掩埋板的顶部边缘自对准的下边缘。
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公开(公告)号：US07138308B2
公开(公告)日：2006-11-21
申请号：US10905070
申请日：2004-12-14
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/3205 , H01L21/4763 , H01L21/302
CPC分类号： H01L29/6656 , H01L29/495 , H01L29/4966 , H01L29/51 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： A field effect transistor formed by a sacrificial gate process has a simplified process and improved yield by using a tunable resistant anti-reflective coating (TERA) as the cap layer over the sacrificial gate layer. The TERA layer serves as a tunable anti-reflection layer for photolithography patterning, a hardmask for etching the sacrificial gate, a polish stopping layer for planarization, and a blocking layer for preventing silicide formation over the sacrificial gate. The TERA is stripped by a two-step process that is highly selective to the nitride spacers, so that the spacers are not damaged in the process of stripping the sacrificial gate.
摘要翻译： 通过牺牲栅极工艺形成的场效应晶体管通过使用可调阻抗抗反射涂层（TERA）作为牺牲栅极层上的覆盖层，具有简化的工艺和提高的产量。 TERA层用作光刻图案的可调谐抗反射层，用于蚀刻牺牲栅极的硬掩模，用于平坦化的抛光停止层，以及用于防止在牺牲栅极上形成硅化物的阻挡层。 通过对氮化物间隔物具有高度选择性的两步法来剥离TERA，使得在剥离牺牲栅极的过程中间隔体不被损坏。
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公开(公告)号：US07132324B2
公开(公告)日：2006-11-07
申请号：US10905002
申请日：2004-12-09
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L29/78642 , H01L27/10864 , H01L27/1087
摘要： A method of forming a memory cell having a trench capacitor and a vertical transistor in a semiconductor substrate includes a step of providing a bonded semiconductor wafer having a lower substrate with an [010] axis parallel to a first wafer axis and an upper semiconductor layer having an [010] axis oriented at forty-five degrees with respect to the wafer axis, the two being connected by a layer of bonding insulator; etching a trench through the upper layer and lower substrate; enlarging the lower portion of the trench and converting the cross section of the upper portion of the trench from octagonal to rectangular, so that sensitivity to alignment errors between the trench lithography and the active area lithography is reduced. An alternative version employs a bonded semiconductor wafer having a lower substrate formed from a (111) crystal structure and the same upper portion. Applications include a vertical transistor that becomes insensitive to misalignment between the trench and the lithographic pattern for the active area, in particular a DRAM cell with a vertical transistor.
摘要翻译： 在半导体衬底中形成具有沟槽电容器和垂直晶体管的存储单元的方法包括提供具有平行于第一晶片轴的[010]轴的下基板的接合半导体晶片的步骤，以及具有 相对于晶片轴线定向成四十五度的[010]轴，两者通过一层粘合绝缘体连接; 蚀刻通过上层和下衬底的沟槽; 扩大沟槽的下部并将沟槽的上部的横截面从八边形转换为矩形，从而降低对沟槽光刻和有源区光刻之间对准误差的敏感性。 替代方案采用具有由（111）晶体结构和相同上部形成的下基板的键合半导体晶片。 应用包括对于有源区域，特别是具有垂直晶体管的DRAM单元对沟槽和光刻图案之间的未对准变得不敏感的垂直晶体管。
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公开(公告)号：US07115934B2
公开(公告)日：2006-10-03
申请号：US10708814
申请日：2004-03-26
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/1087 , H01L21/31111 , H01L29/66181 , H01L29/945
摘要： A trench capacitor formed with a bottle etch step has a polygonal cross section produced by forming thermally oxidizing the trench walls with thinner oxide at the corners of the trench, then performing the bottle etch step with the nitride in place, thereby extending the trench walls laterally only outside the corners, so that the distance of closest approach between adjacent trenches is reduced while the length of the perimeter is maintained.
摘要翻译： 形成有瓶蚀刻步骤的沟槽电容器具有通过在沟槽的拐角处以较薄氧化物热交换沟槽壁而产生的多边形横截面，然后在氮化物就位的情况下执行瓶蚀刻步骤，从而将沟槽壁横向延伸 仅在角落之外，使得相邻沟槽之间最接近的距离减小，同时保持周长的长度。
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