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91.发明申请Register Indirect Access of Program Floating Point Registers by Millicode 失效通过Millicode寄存器间接访问程序浮点寄存器公开(公告)号：US20080126759A1
公开(公告)日：2008-05-29
申请号：US11531301
申请日：2006-09-13
IPC分类号： G06F9/302
CPC分类号： G06F9/3017 , G06F9/35
摘要： Complex floating point instructions are executed under millicode control when it is not cost effective to implement its function in hardware. One of the disadvantages to executing complex instructions using millicode routines is that determining and accessing the instructions operands are costly for millicode performance. To determine what the source and target location are, the instruction text is parsed. Furthermore the millicode instruction stream must be modified to access the operand data from and write the result to the program registers specified by the complex floating point instruction. The invention overcomes these disadvantages by providing millicode with register indirect access to the program floating point registers.
摘要翻译： 当在硬件中实现其功能不具有成本效益时，复杂的浮点指令在毫秒控制下执行。 使用millicode例程执行复杂指令的一个缺点是确定和访问指令操作数对于millicode性能来说是昂贵的。 要确定源和目标位置是什么，解释说明文本。 此外，必须修改millicode指令流以访问操作数数据，并将结果写入由复杂浮点指令指定的程序寄存器。 本发明通过向编程浮点寄存器提供寄存器间接访问的毫代码来克服这些缺点。
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公开(公告)号：US07082550B2
公开(公告)日：2006-07-25
申请号：US10435914
申请日：2003-05-12
IPC分类号： G06F11/16
CPC分类号： G06F11/1695 , G06F11/1641
摘要： A processor responsive to a clock cycle includes a base-unit, a mirror-unit that is a duplicate instance of the base-unit, a non-duplicate-unit in signal communication with the base and mirror units, a first staging register disposed at the input to the mirror-unit for delaying the input signal thereto by at least one clock cycle, and a second staging register disposed at the output of the mirror-unit for delaying the output signal therefrom by at least one clock cycle. The non-duplicate-unit includes a comparator for comparing the output signals of the base and mirror units.
摘要翻译： 响应于时钟周期的处理器包括基本单元，作为基本单元的重复实例的镜像单元，与基础单元和镜像单元进行信号通信的非重复单元，第一分段寄存器，其布置在 用于将输入信号延迟至少一个时钟周期的反射镜单元的输入，以及设置在镜单元的输出处的第二分段寄存器，用于将其输出信号延迟至少一个时钟周期。 非重复单元包括用于比较基座和反射镜单元的输出信号的比较器。
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93.发明授权公开(公告)号：US07082517B2
公开(公告)日：2006-07-25
申请号：US10435806
申请日：2003-05-12
CPC分类号： G06F9/3017 , G06F9/3836 , G06F9/3885
摘要： In a computer system for use as a symetrical multiprocessor, a superscalar microprocessor apparatus allows dispatching and executing multi-cycle and complex instructions Some control signals are generated in the dispatch unit and dispatched with the instruction to the Fixed Point Unit (FXU). Multiple execution pipes correspond to the instruction dispatch ports and the execution unit is a Fixed Point Unit (FXU) which contains three execution dataflow pipes (X, Y and Z) and one control pipe (R). The FXU logic then execute these instructions on the available FXU pipes. This results in optimum performance with little or no other complications. The presented technique places the flexibility of how these instructions will be executed in the FXU, where the actual execution takes place, instead of in the instruction decode or dispatch units or cracking by the compiler.
摘要翻译： 在用作对称多处理器的计算机系统中，超标量微处理器装置允许调度和执行多周期和复杂指令。在调度单元中生成一些控制信号，并且通过指令发送到定点单元（FXU）。 多个执行管道对应于指令调度端口，执行单元是包含三个执行数据流管道（X，Y和Z）和一个控制管道（R）的定点单元（FXU）。 然后，FXU逻辑在可用的FXU管道上执行这些说明。 这导致最佳性能，很少或没有其他并发症。 所提出的技术使得如何在实际执行的FXU中执行这些指令的灵活性，而不是在指令解码或调度单元中或由编译器破解。
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公开(公告)号：US5282210A
公开(公告)日：1994-01-25
申请号：US891521
申请日：1992-06-01
CPC分类号： H04J3/047
摘要： A time-division multiplex system is disclosed where the data from two sources is coupled over a multiplexer controller by a generator comprising an XOR gate and a pair of latches where the output of both latches are coupled to the XOR gate and an inverter at the input of each latch. One of the latches is gated by a master clock signal and the other latch is gated by a clocked signal skewed approximately one-half clock cycle.
摘要翻译： 公开了一种时分多路复用系统，其中来自两个源的数据通过多路复用器控制器由包括XOR门和一对锁存器的发生器耦合，其中两个锁存器的输出耦合到XOR门和在输入端的反相器 的每个闩锁。 一个锁存器由主时钟信号门控，另一个锁存器由大约半个时钟周期的时钟信号门控。
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公开(公告)号：US10656945B2
公开(公告)日：2020-05-19
申请号：US13524105
申请日：2012-06-15
申请人： Christian Jacobi , Chung-Lung Kevin Chum , Timothy J. Slegel , Gustav E. Sittmann, III , Cynthia Sittmann
IPC分类号： G06F9/34 , G06F12/123 , G06F9/30 , G06F12/0815 , G06F12/126 , G06F12/0862 , G06F9/38
摘要： Executing a Next Instruction Access Intent instruction by a computer. The processor obtains an access intent instruction indicating an access intent. The access intent is associated with an operand of a next sequential instruction. The access intent indicates usage of the operand by one or more instructions subsequent to the next sequential instruction. The computer executes the access intent instruction. The computer obtains the next sequential instruction. The computer executes the next sequential instruction, whose execution comprises, based on the access intent, adjusting one or more cache behaviors for the operand of the next sequential instruction.
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96.发明授权Copying character data having a termination character from one memory location to another 有权将具有终止字符的字符数据从一个存储器位置复制到另一个存储器位置公开(公告)号：US09454366B2
公开(公告)日：2016-09-27
申请号：US13421498
申请日：2012-03-15
CPC分类号： G06F9/30018 , G06F9/30021 , G06F9/30036 , G06F9/30043
摘要： Copying characters of a set of terminated character data from one memory location to another memory location using parallel processing and without causing unwarranted exceptions. The character data to be copied is loaded within one or more vector registers. In particular, in one embodiment, an instruction (e.g., a Vector Load to block Boundary instruction) is used that loads data in parallel in a vector register to a specified boundary, and provides a way to determine the number of characters loaded. To determine the number of characters loaded (a count), another instruction (e.g., a Load Count to Block Boundary instruction) is used. Further, an instruction (e.g., a Vector Find Element Not Equal instruction) is used to find the index of the first delimiter character, i.e., the first termination character, such as a zero or null character within the character data. This instruction checks a plurality of bytes of data in parallel.
摘要翻译： 使用并行处理将一组终止的字符数据的字符从一个存储器位置复制到另一个存储器位置，并且不引起无理的异常。 要复制的字符数据被加载到一个或多个向量寄存器中。 特别地，在一个实施例中，使用将矢量寄存器中并行的数据加载到指定边界的指令（例如，向量块向量边界指令），并且提供了确定加载的字符数的方法。 为了确定加载的字符数（计数），使用另一条指令（例如，向块边界指令的加载计数）。 此外，使用指令（例如，矢量查找元素不等于指令）来找到第一分隔符字符的索引，即第一终止字符，例如字符数据内的零或空字符。 该指令并行地检查多个字节的数据。
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公开(公告)号：US09442737B2
公开(公告)日：2016-09-13
申请号：US13524833
申请日：2012-06-15
申请人： Khary J. Alexander , Brenton F. Belmar , Christian Jacobi , Randall W. Philley , Anthony Saporito , Timothy J. Slegel
发明人： Khary J. Alexander , Brenton F. Belmar , Christian Jacobi , Randall W. Philley , Anthony Saporito , Timothy J. Slegel
CPC分类号： G06F9/3861 , G06F9/3004 , G06F9/30087 , G06F9/38 , G06F9/3857 , G06F9/466 , G06F9/467 , G06F9/52 , G06F9/524
摘要： Processing of transactions within a computing environment is facilitated by taking actions to increase the chances of successfully executing a transaction. A counter is maintained that provides a count of how often a transaction has aborted. The counter increments the count each time the transaction is aborted, and it is reset to zero upon successful completion of the transaction or an interruption leading to no more re-executions of the transaction. If the count reaches a threshold value, then an interrupt is presented and transaction execution is unsuccessful. However, before the count reaches the threshold, a number of actions may be taken to increase the chances of successfully executing the transaction. These actions include actions to be performed within the processor executing the transaction, and/or actions to be performed against conflicting processors.
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公开(公告)号：US09367323B2
公开(公告)日：2016-06-14
申请号：US13524871
申请日：2012-06-15
CPC分类号： G06F9/3861 , G06F9/3004 , G06F9/30087 , G06F9/3842 , G06F9/3857 , G06F9/466
摘要： An operation is provided to signal a processor that action is to be taken to facilitate execution of a transaction that has aborted one or more times. The operation is specified within an instruction or is itself an instruction. The instruction is executed based on detecting an abort of the transactions, and includes a field indicating how many times the transaction has aborted. The processor uses this information to determine what action is to be taken.
摘要翻译： 提供了一种操作来向处理器发出信号，该操作将采取行动来促进已经中止一次或多次的事务的执行。 操作在指令中指定或本身是指令。 该指令是基于检测到事务中止而执行的，并且包括指示事务中止多少次的字段。 处理器使用这些信息来确定要采取的行动。
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公开(公告)号：US09317460B2
公开(公告)日：2016-04-19
申请号：US13524903
申请日：2012-06-15
CPC分类号： G06F13/24 , G06F9/466 , G06F11/3636
摘要： A transaction is initiated within a computing environment, and based on detecting a program event recording event, an interrupt is presented for the transaction. Subsequent to the interrupt, one or more controls are set to inhibit presentation of another interrupt based on detecting another PER event. Thereafter, the transaction is re-executed and PER events detected during execution of the transaction are ignored.
摘要翻译： 事务在计算环境内启动，并且基于检测到程序事件记录事件，为事务呈现中断。 在中断之后，一个或多个控制被设置为基于检测另一个PER事件来抑制另一中断的呈现。 此后，事务被重新执行，并且在执行事务期间检测到的PER事件被忽略。
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公开(公告)号：US09280447B2
公开(公告)日：2016-03-08
申请号：US13422598
申请日：2012-03-16
CPC分类号： G06F11/3644 , G06F9/30076 , G06F9/30101 , G06F11/3636 , G06F11/3648
摘要： Embodiments of the invention relate to modifying run-time-instrumentation controls (MRIC) from a lesser-privileged state. The MRIC instruction is fetched. The MRIC instruction includes the address of a run-time-instrumentation control block (RICCB). The RICCB is fetched based on the address included in the MRIC instruction. The RICCB includes values for modifying a subset of the processor's run-time-instrumentation controls. The subset of run-time-instrumentation controls includes a runtime instrumentation program buffer current address (RCA) of a runtime instrumentation program buffer (RIB) location. The RIB holds run-time-instrumentation information of the events recognized by the processor during program execution. The values of the RICCB are loaded into the run-time-instrumentation controls. Event information is provided to the RIB based on the values that were loaded in the run-time-instrumentation control.
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