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    Semiconductor integrated circuit device having power reduction mechanism
    92.
    发明授权
    Semiconductor integrated circuit device having power reduction mechanism 失效
    具有功率降低机构的半导体集成电路装置

    公开(公告)号：US06404239B1

    公开(公告)日：2002-06-11

    申请号：US09613594

    申请日：2000-07-10

    申请人： Takayuki Kawahara ,  Ryoichi Hori ,  Masashi Horiguchi ,  Ryoichi Kurihara ,  Kiyoo Itoh ,  Masakazu Aoki ,  Takeshi Sakata ,  Kunio Uchiyama

    发明人： Takayuki Kawahara ,  Ryoichi Hori ,  Masashi Horiguchi ,  Ryoichi Kurihara ,  Kiyoo Itoh ,  Masakazu Aoki ,  Takeshi Sakata ,  Kunio Uchiyama

    IPC分类号： H03K1920

    CPC分类号： H03K3/356113 ,  H01L27/0218 ,  H03K19/0016

    摘要： A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.

    摘要翻译： 半导体集成电路器件由各自设置有至少两个MOS晶体管的逻辑门组成。 逻辑门连接到第一电势点和第二电位点。 半导体集成电路装置包括连接在逻辑门与第一电位点之间和/或逻辑门与第二电势点之间的电流控制装置，用于根据操作状态控制在逻辑门中流动的电流的值 逻辑门。 该电路可用于在高功耗模式和低功耗模式之间循环运行的器件，例如具有用于功率降低的操作模式和低功率备用或睡眠模式的微处理器。

    Semiconductor device having redundancy circuit
    93.
    发明授权
    Semiconductor device having redundancy circuit 失效
    具有冗余电路的半导体器件

    公开(公告)号：US06337817B1

    公开(公告)日：2002-01-08

    申请号：US09633271

    申请日：2000-08-04

    申请人： Masashi Horiguchi ,  Jun Etoh ,  Masakazu Aoki ,  Kiyoo Itoh

    发明人： Masashi Horiguchi ,  Jun Etoh ,  Masakazu Aoki ,  Kiyoo Itoh

    IPC分类号： G11C700

    CPC分类号： G11C29/80 ,  G11C29/785 ,  G11C29/808

    摘要： A semiconductor memory such as a dynamic random access memory (DRAM), having a memory array which is divided into memory mats and a storage capacity of 16 M bits or more, features a defect recovery scheme through employing a redundancy circuit. The memory array in the memory has a plurality of word lines, a plurality of bit lines, a spare bit line, and a plurality of memory cells. The redundancy circuit includes a comparing circuit having programmable elements which function as a memory for storing therein a defective address existing in the memory array. The programmable elements of the redundancy circuit can be programmed in accordance with any of a number of different types of defect modes. In accordance with this, each comparing circuit of the redundancy circuit compares information (data) inputted therein, for example, the column and row addresses which may be under the control of an address multiplex system, with that programmed in the programmable elements of the comparing circuit. On the basis of this comparison, an appropriate defect recovery is effected

    摘要翻译： 诸如动​​态随机存取存储器（DRAM）的半导体存储器具有分割成存储器存储器的存储器阵列和16M位或更多存储容量的特征，通过采用冗余电路来形成缺陷恢复方案。 存储器中的存储器阵列具有多个字线，多个位线，备用位线和多个存储器单元。 冗余电路包括具有可编程元件的比较电路，其作为用于在其中存储存储器阵列中存在的缺陷地址的存储器。 冗余电路的可编程元件可以根据多种不同类型的缺陷模式中的任何一种进行编程。 根据这一点，冗余电路的每个比较电路比较输入其中的信息（数据），例如可能在地址多路复用系统的控制下的列和行地址与在比较的可编程元件中编程的 电路。 在此比较的基础上，进行适当的缺陷恢复

    Semiconductor device having redundancy circuit
    95.
    发明授权
    Semiconductor device having redundancy circuit 失效
    具有冗余电路的半导体器件

    公开(公告)号：US6104647A

    公开(公告)日：2000-08-15

    申请号：US363000

    申请日：1999-07-30

    申请人： Masashi Horiguchi ,  Jun Etoh ,  Masakazu Aoki ,  Kiyoo Itoh

    发明人： Masashi Horiguchi ,  Jun Etoh ,  Masakazu Aoki ,  Kiyoo Itoh

    IPC分类号： G11C5/00 ,  G11C7/00 ,  G11C8/00 ,  G11C29/00

    CPC分类号： G11C29/80 ,  G11C29/785 ,  G11C29/808

    摘要： A redundancy technique is introduced for a semiconductor memory and, more particularly, a redundancy technique for a memory, for example, a dynamic random access memory (DRAM) having a memory array which is divided into memory mats and a storage capacity of 16 mega bits or more. According to the present redundancy technique, for a semiconductor memory including a memory array which has a plurality of word lines, a plurality of bit lines arranged so that two-level crossings are formed between the word lines and the bit lines, memory cells disposed at desired ones of the two-level crossings, and spare bit lines, there is provided a redundancy circuit having a memory for storing therein a defective address existing in the memory array and comparing an address to be accessed with the stored defective address. Each of the address comparing circuits as stored therein the column address of a defective bit line and a part of the row address indicating the memory mat corresponding to the defective bit line.

    摘要翻译： 为半导体存储器引入冗余技术，更具体地说，涉及一种用于存储器的冗余技术，例如具有存储器阵列的动态随机存取存储器（DRAM），该存储器阵列被分成存储器阵列，存储容量为16兆比特 或者更多。 根据本技术的冗余技术，对于包含具有多个字线的存储器阵列的半导体存储器，配置成在字线和位线之间形成2级交叉的多位位线，位于 提供了两级交叉中的期望的和备用位线，提供了一种冗余电路，其具有用于在其中存储存在于存储器阵列中的缺陷地址并将要访问的地址与存储的缺陷地址进行比较的存储器。 每个地址比较电路存储有缺陷位线的列地址和表示与缺陷位线对应的存储器堆的行地址的一部分。

    Semiconductor integrated circuit device having power reduction mechanism
    100.
    发明授权
    Semiconductor integrated circuit device having power reduction mechanism 失效
    具有降压机构的半导体集成电路装置

    公开(公告)号：US07750668B2

    公开(公告)日：2010-07-06

    申请号：US11979100

    申请日：2007-10-31

    申请人： Masashi Horiguchi ,  Kunio Uchiyama ,  Kiyoo Itoh ,  Takeshi Sakata ,  Masakazu Aoki ,  Takayuki Kawahara

    发明人： Masashi Horiguchi ,  Kunio Uchiyama ,  Kiyoo Itoh ,  Takeshi Sakata ,  Masakazu Aoki ,  Takayuki Kawahara

    IPC分类号： H03K19/003 ,  G05F1/10 ,  G06F1/32

    CPC分类号： H01L27/0207 ,  G06F1/3203 ,  G11C5/14 ,  H01L27/0218 ,  H03K3/356113 ,  H03K19/0013 ,  H03K19/0016 ,  H03K19/01721

    摘要： A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.

    摘要翻译： 半导体集成电路器件由各自设置有至少两个MOS晶体管的逻辑门组成。 逻辑门连接到第一电势点和第二电位点。 半导体集成电路装置包括连接在逻辑门与第一电位点之间和/或逻辑门与第二电势点之间的电流控制装置，用于根据操作状态控制在逻辑门中流动的电流的值 逻辑门。 该电路可用于在高功耗模式和低功耗模式之间循环运行的器件，例如具有用于功率降低的操作模式和低功率备用或睡眠模式的微处理器。