公开(公告)号：US08371781B2

公开(公告)日：2013-02-12

申请号：US12822158

申请日：2010-06-23

申请人： Philippe Roy ,  Peter Driessen ,  Vishwanath Bhat

发明人： Philippe Roy ,  Peter Driessen ,  Vishwanath Bhat

IPC分类号： B60P7/08

CPC分类号： B64D11/0696 ,  Y10T29/49947 ,  Y10T403/32467

摘要： Described are track fitting assemblies having a main body, at least one pre-loaded stud assembly, and a track comprising a pair of lips. The at least one pre-loaded stud assembly includes a stud and a compressing device, wherein the stud does not contact the compressing device in a clamped position and does not contact the pair of lips in an unclamped position. As examples, track fitting assemblies also include at least one shear plunger assembly having a shear pin and a button, wherein the button extends from the main body and the shear pin is positioned within the main body in a disengaged position, and the button is positioned flush with the main body and the shear pin is extended from the main body in an engaged position.

摘要翻译： 描述的是具有主体，至少一个预加载螺柱组件和包括一对唇缘的轨道的轨道装配组件。 所述至少一个预加载螺柱组件包括螺柱和压缩装置，其中所述螺柱在夹紧位置不接触所述压缩装置，并且在未夹紧位置不接触所述一对唇缘。 作为示例，轨道装配组件还包括至少一个具有剪切销和按钮的剪切柱塞组件，其中按钮从主体延伸并且剪切销位于主体内处于脱离位置，并且按钮被定位 与主体齐平并且剪切销从主体在接合位置延伸。

公开(公告)号：US20130011990A1

公开(公告)日：2013-01-10

申请号：US13614854

申请日：2012-09-13

申请人： Vishwanath Bhat ,  Rishikesh Krishnan ,  Daniel Gealy

发明人： Vishwanath Bhat ,  Rishikesh Krishnan ,  Daniel Gealy

IPC分类号： H01L21/02 ,  H01L21/316

CPC分类号： C23C16/405 ,  C30B25/02 ,  C30B29/16 ,  H01G4/33 ,  H01G9/0032 ,  H01L28/65

摘要： There is disclosed a method of forming crystalline tantalum pentoxide on a ruthenium-containing material having an oxygen-containing surface wherein the oxygen-containing surface is contacted with a treating composition, such as water, to remove at least some oxygen. Crystalline tantalum pentoxide is formed on at least a portion of the surface having reduced oxygen content.

摘要翻译： 公开了在具有含氧表面的含钌材料上形成结晶五氧化钽的方法，其中含氧表面与处理组合物如水接触以除去至少一些氧。 在具有降低的氧含量的表面的至少一部分上形成五氧化二钽结晶。

公开(公告)号：US08282988B2

公开(公告)日：2012-10-09

申请号：US13210836

申请日：2011-08-16

申请人： Vishwanath Bhat ,  Rishikesh Krishnan ,  Daniel F. Gealy

发明人： Vishwanath Bhat ,  Rishikesh Krishnan ,  Daniel F. Gealy

IPC分类号： B05D5/12 ,  C23C16/00

CPC分类号： C23C16/405 ,  C30B25/02 ,  C30B29/16 ,  H01G4/33 ,  H01G9/0032 ,  H01L28/65

摘要： There is disclosed a method of forming crystalline tantalum pentoxide on a ruthenium-containing material having an oxygen-containing surface wherein the oxygen-containing surface is contacted with a treating composition, such as water, to remove at least some oxygen. Crystalline tantalum pentoxide is formed on at least a portion of the surface having reduced oxygen content.

摘要翻译： 公开了在具有含氧表面的含钌材料上形成结晶五氧化钽的方法，其中含氧表面与处理组合物如水接触以除去至少一些氧。 在具有降低的氧含量的表面的至少一部分上形成五氧化二钽结晶。

公开(公告)号：US08110469B2

公开(公告)日：2012-02-07

申请号：US11216542

申请日：2005-08-30

申请人： Dan Gealy ,  Vishwanath Bhat ,  Cancheepuram V. Srividya ,  M. Noel Rocklein

发明人： Dan Gealy ,  Vishwanath Bhat ,  Cancheepuram V. Srividya ,  M. Noel Rocklein

IPC分类号： H01L21/336 ,  H01L21/3205 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/022 ,  C23C16/45529 ,  H01L21/02148 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/28194 ,  H01L21/3141 ,  H01L21/3142 ,  H01L21/31641 ,  H01L21/31645 ,  H01L28/40 ,  H01L28/56 ,  H01L29/517 ,  H01L29/78

摘要： Graded dielectric layers and methods of fabricating such dielectric layers provide dielectrics in a variety of electronic structures for use in a wide range of electronic devices and systems. In an embodiment, a dielectric layer is graded with respect to a doping profile across the dielectric layer. In an embodiment, a dielectric layer is graded with respect to a crystalline structure profile across the dielectric layer. In an embodiment, a dielectric layer is formed by atomic layer deposition incorporating sequencing techniques to generate a doped dielectric material.

摘要翻译： 梯度介电层和制造这种电介质层的方法在各种电子结构中提供电介质以用于广泛的电子设备和系统。 在一个实施例中，电介质层相对于跨介电层的掺杂分布而分级。 在一个实施例中，电介质层相对于介电层上的晶体结构分布呈梯度分布。 在一个实施例中，通过包含测序技术的原子层沉积形成电介质层以产生掺杂的电介质材料。

公开(公告)号：US08012532B2

公开(公告)日：2011-09-06

申请号：US11958952

申请日：2007-12-18

申请人： Vishwanath Bhat ,  Rishikesh Krishnan ,  Dan Gealy

发明人： Vishwanath Bhat ,  Rishikesh Krishnan ,  Dan Gealy

IPC分类号： B05D5/12 ,  B05D3/00 ,  B05D3/04 ,  C23C14/02 ,  H05H1/00

CPC分类号： C23C16/405 ,  C30B25/02 ,  C30B29/16 ,  H01G4/33 ,  H01G9/0032 ,  H01L28/65

摘要： There is disclosed a method of forming crystalline tantalum pentoxide on a ruthenium-containing material having an oxygen-containing surface wherein the oxygen-containing surface is contacted with a treating composition, such as water, to remove at least some oxygen. Crystalline tantalum pentoxide is formed on at least a portion of the surface having reduced oxygen content.

摘要翻译： 公开了在具有含氧表面的含钌材料上形成结晶五氧化钽的方法，其中含氧表面与处理组合物如水接触以除去至少一些氧。 在具有降低的氧含量的表面的至少一部分上形成五氧化二钽结晶。

公开(公告)号：US07820506B2

公开(公告)日：2010-10-26

申请号：US12251733

申请日：2008-10-15

申请人： Noel Rocklein ,  Chris M. Carlson ,  Dave Peterson ,  Cunyu Yang ,  Praveen Vaidyanathan ,  Vishwanath Bhat

发明人： Noel Rocklein ,  Chris M. Carlson ,  Dave Peterson ,  Cunyu Yang ,  Praveen Vaidyanathan ,  Vishwanath Bhat

IPC分类号： H01L29/92

CPC分类号： H01L21/28273 ,  H01L21/02175 ,  H01L21/02194 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/3142 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/91 ,  H01L29/51 ,  H01L29/513 ,  H01L29/78

摘要： Some embodiments include dielectric structures. The structures include first and second portions that are directly against one another. The first portion may contain a homogeneous mixture of a first phase and a second phase. The first phase may have a dielectric constant of greater than or equal to 25, and the second phase may have a dielectric constant of less than or equal to 20. The second portion may be entirely a single composition having a dielectric constant of greater than or equal to 25. Some embodiments include electrical components, such as capacitors and transistors, containing dielectric structures of the type described above. Some embodiments include methods of forming dielectric structures, and some embodiments include methods of forming electrical components.

摘要翻译： 一些实施例包括电介质结构。 这些结构包括彼此直接相对的第一和第二部分。 第一部分可以包含第一相和第二相的均匀混合物。 第一相可以具有大于或等于25的介电常数，并且第二相可以具有小于或等于20的介电常数。第二部分可以是完全是具有大于或等于20的介电常数的单一组成， 等于25.一些实施例包括包含上述类型的电介质结构的电气部件，例如电容器和晶体管。 一些实施方案包括形成电介质结构的方法，并且一些实施方案包括形成电组件的方法。

公开(公告)号：US20100151653A1

公开(公告)日：2010-06-17

申请号：US12710077

申请日：2010-02-22

申请人： Vishwanath Bhat ,  Kevin R. Shea ,  Farrell Good

发明人： Vishwanath Bhat ,  Kevin R. Shea ,  Farrell Good

IPC分类号： H01L21/02

CPC分类号： H01L27/10894 ,  H01L27/10852 ,  H01L28/91

摘要： A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations. The intervening area comprises a trench. Conductive material is formed within the openings and against a sidewall portion of the trench to less than completely fill the trench. Covering material is formed over an elevationally outer lateral interface of the conductive material within the trench and the insulative material of the circuitry area. The insulative material within the array area is etched with a liquid etching solution effective to expose outer sidewall portions of the conductive material within the array area and to expose the conductive material within the trench. The conductive material within the array area is incorporated into a plurality of capacitors.

摘要翻译： 形成多个电容器的方法包括在电容器阵列区域和电路区域上接收的绝缘材料。 阵列区域包括在单独的电容器存储节点位置处接收的绝缘材料内的多个电容器电极开口。 中间区域包括沟槽。 导电材料形成在开口内并抵靠沟槽的侧壁部分，以小于完全填充沟槽。 覆盖材料形成在沟槽内的导电材料的正面外侧界面和电路区域的绝缘材料之间。 用液体蚀刻溶液蚀刻阵列区域内的绝缘材料，该液体蚀刻溶液有效地暴露阵列区域内的导电材料的外侧壁部分并露出沟槽内的导电材料。 阵列区域内的导电材料被并入多个电容器中。

公开(公告)号：US07682924B2

公开(公告)日：2010-03-23

申请号：US11838070

申请日：2007-08-13

申请人： Vishwanath Bhat ,  Kevin R. Shea ,  Farrell Good

发明人： Vishwanath Bhat ,  Kevin R. Shea ,  Farrell Good

IPC分类号： H01L21/20

CPC分类号： H01L27/10894 ,  H01L27/10852 ,  H01L28/91

摘要： A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations. The intervening area comprises a trench. Conductive material is formed within the openings and against a sidewall portion of the trench to less than completely fill the trench. Covering material is formed over an elevationally outer lateral interface of the conductive material within the trench and the insulative material of the circuitry area. The insulative material within the array area is etched with a liquid etching solution effective to expose outer sidewall portions of the conductive material within the array area and to expose the conductive material within the trench. The conductive material within the array area is incorporated into a plurality of capacitors.

摘要翻译： 形成多个电容器的方法包括在电容器阵列区域和电路区域上接收的绝缘材料。 阵列区域包括在单独的电容器存储节点位置处接收的绝缘材料内的多个电容器电极开口。 中间区域包括沟槽。 导电材料形成在开口内并抵靠沟槽的侧壁部分，以小于完全填充沟槽。 覆盖材料形成在沟槽内的导电材料的正面外侧界面和电路区域的绝缘材料之间。 用液体蚀刻溶液蚀刻阵列区域内的绝缘材料，该液体蚀刻溶液有效地暴露阵列区域内的导电材料的外侧壁部分并露出沟槽内的导电材料。 阵列区域内的导电材料被并入多个电容器中。

公开(公告)号：US20100025362A1

公开(公告)日：2010-02-04

申请号：US12575263

申请日：2009-10-07

申请人： Kevin Shea ,  Brett Busch ,  Farrell Good ,  Irina Vasilyeva ,  Vishwanath Bhat

发明人： Kevin Shea ,  Brett Busch ,  Farrell Good ,  Irina Vasilyeva ,  Vishwanath Bhat

IPC分类号： C23F1/00 ,  B32B37/00 ,  H01L21/02

CPC分类号： H01L27/10852 ,  H01L27/10894 ,  H01L28/91 ,  Y10T156/10

摘要： A method of forming a capacitor includes providing material having an opening therein over a node location on a substrate. A shield is provided within and across the opening, with a void being received within the opening above the shield and a void being received within the opening below the shield. The shield comprises a nitride. Etching is conducted within the opening through the nitride-comprising shield. After the etching, a first capacitor electrode is formed within the opening in electrical connection with the node location. A capacitor dielectric and a second capacitor electrode are formed operatively adjacent the first capacitor electrode. Other aspects and implementations are contemplated.

摘要翻译： 形成电容器的方法包括在衬底上的节点位置上提供其中具有开口的材料。 在开口内和横过开口设置有屏蔽件，空隙被容纳在屏蔽件上方的开口内，并且在屏蔽件下面的开口内容纳有空隙。 屏蔽包括氮化物。 通过包含氮化物的护罩在开口内进行蚀刻。 在蚀刻之后，在开口内形成与节点位置电连接的第一电容器电极。 与第一电容器电极可操作地形成电容器电介质和第二电容器电极。 考虑了其他方面和实现。

公开(公告)号：US20060234502A1

公开(公告)日：2006-10-19

申请号：US11105096

申请日：2005-04-13

申请人： Vishwanath Bhat ,  F. Gealy

发明人： Vishwanath Bhat ,  F. Gealy

IPC分类号： H01L21/44

CPC分类号： H01L21/28556 ,  H01L21/28088 ,  H01L27/10852 ,  H01L28/40 ,  H01L29/4966 ,  H01L29/78

摘要： The present invention is generally directed to a method of forming titanium nitride layers. In one illustrative embodiment, the method includes forming a layer of titanium nitride by performing a deposition process, performing an anneal process on the layer of titanium nitride in a chlorine scavenging ambient to define an annealed layer of titanium nitride, and, prior to exposing the annealed layer of titanium nitride to an oxygen-containing ambient, forming a cap layer on the annealed layer of titanium nitride. In another illustrative embodiment, the method includes performing a chemical vapor deposition process in a first process chamber to form a layer of titanium nitride above a semiconducting substrate, transferring the substrate to a second process chamber, performing an anneal process on the layer of titanium nitride in a chlorine scavenging ambient within the second process chamber to produce an anneal layer of titanium nitride, and, prior to exposing the annealed layer of titanium nitride to an oxygen-containing ambient, forming a cap layer on the annealed layer of titanium nitride in the second process chamber.

摘要翻译： 本发明一般涉及形成氮化钛层的方法。 在一个说明性实施例中，该方法包括通过执行沉积工艺形成氮化钛层，在氯清除环境中对氮化钛层进行退火处理以限定氮化钛的退火层，并且在暴露 将退火的氮化钛层与含氧环境反应，在氮化钛的退火层上形成覆盖层。 在另一说明性实施例中，该方法包括在第一处理室中进行化学气相沉积工艺以在半导体衬底上形成氮化钛层，将衬底转移到第二工艺室，对氮化钛层进行退火处理 在第二处理室内的氯清除环境中，以产生氮化钛的退火层，并且在将退火的氮化钛层暴露于含氧环境之前，在氮化钛的退火层上形成覆盖层 第二处理室。