公开(公告)号：US20080277696A1

公开(公告)日：2008-11-13

申请号：US12179320

申请日：2008-07-24

申请人： Kazuhiro Fujikawa ,  Shin Harada ,  Kenichi Hirotsu ,  Satoshi Hatsukawa ,  Takashi Hoshino ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

发明人： Kazuhiro Fujikawa ,  Shin Harada ,  Kenichi Hirotsu ,  Satoshi Hatsukawa ,  Takashi Hoshino ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

IPC分类号： H01L29/808

CPC分类号： H01L29/0634 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/42316 ,  H01L29/66893 ,  H01L29/808

摘要： A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.

摘要翻译： 横向结型场效应晶体管包括布置在源/漏区域之间的第三半导体层中的第一栅电极层，具有在第二半导体层上延伸的下表面，并且掺杂有比第二半导体层更重的p型杂质 以及布置在源极/漏极区域之间的第五半导体层中的第二栅极电极层，具有在第四半导体层上延伸的下表面，具有与第一栅极电极层基本相同的p型杂质浓度，以及 具有与第一栅极电极层相同的电位。 因此，横向结型场效应晶体管具有可以在保持良好的击穿电压特性的同时降低导通电阻的结构。

公开(公告)号：US20070243893A1

公开(公告)日：2007-10-18

申请号：US11712493

申请日：2007-03-01

申请人： Kazuhiro Takahashi ,  Yoshihiro Ono ,  Shin Harada ,  Takashi Shiraki ,  Takehiko Kashiwagi ,  Junpei Kamimura

发明人： Kazuhiro Takahashi ,  Yoshihiro Ono ,  Shin Harada ,  Takashi Shiraki ,  Takehiko Kashiwagi ,  Junpei Kamimura

IPC分类号： H04B7/00

CPC分类号： H04W4/10 ,  H04W72/005 ,  H04W76/45 ,  H04W88/14 ,  H04W88/18

摘要： The object of the present invention is to realize a method and a server which enable insertion of advertisement even in voice communication including multimedia communication. The server is configured as a server for managing PoC communication among multiple terminals, comprising: a right-to-speak management section for managing the right to speak of the multiple terminals; a data distribution section for transmitting and receiving data to and from the multiple terminals; and an advertisement control section for storing advertisement data and transmitting the stored advertisement data to the multiple terminals via the data distribution section.

摘要翻译： 本发明的目的是实现即使在包括多媒体通信的语音通信中也能插入广告的方法和服务器。 该服务器被配置为用于管理多个终端之间的PoC通信的服务器，包括：用于管理多个终端的发言权的一个发言权管理部分; 数据分配部，用于向多个终端发送数据和从多个终端接收数据; 以及广告控制部分，用于存储广告数据并经由数据分发部分将存储的广告数据发送到多个终端。

公开(公告)号：US06870189B1

公开(公告)日：2005-03-22

申请号：US10168265

申请日：2000-09-11

申请人： Shin Harada ,  Kenichi Hirotsu ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

发明人： Shin Harada ,  Kenichi Hirotsu ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

IPC分类号： H01L21/337 ,  H01L29/24 ,  H01L29/772 ,  H01L29/808 ,  H01L31/0312 ,  H01L29/80 ,  H01L31/112

CPC分类号： H01L29/0843 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/66901 ,  H01L29/66909 ,  H01L29/7722 ,  H01L29/808 ,  H01L29/8083

摘要： A junction field effect transistor (JFET) is provided that is capable of a high voltage resistance, high current switching operation, that operates with a low loss, and that has little variation. This JFET is provided with a gate region (2) of a second conductivity type provided on a surface of a semiconductor substrate, a source region (1) of a first conductivity type, a channel region (10) of the first conductivity type that adjoins the source region, a confining region (5) of the second conductivity type that adjoins the gate region and confines the channel region, a drain region (3) of the first conductivity type provided on a reverse face, and a drift region (4) of the first conductivity type that continuously lies in a direction of thickness of the substrate from a channel to a drain. A concentration of an impurity of the first conductivity type in the drift region and the channel region is lower than a concentration of an impurity of the first conductivity type in the source region and the drain region and a concentration of an impurity of the second conductivity type in the confining region.

摘要翻译： 提供了一种结型场效应晶体管（JFET），其具有能够以低损耗工作并且几乎没有变化的高电压电阻，高电流切换操作。 该JFET设置有设置在半导体衬底的表面上的第二导电类型的栅极区域（2），第一导电类型的源极区域（1），第一导电类型的沟道区域（10） 源极区域，邻接栅极区域并限制沟道区域的第二导电类型的约束区域（5），设置在反面上的第一导电类型的漏极区域（3）和漂移区域（4） 的第一导电类型，其连续地位于从通道到漏极的衬底的厚度方向上。 漂移区域和沟道区域中的第一导电类型的杂质的浓度低于源极区域和漏极区域中的第一导电类型的杂质浓度和第二导电类型的杂质浓度 在限制区域。

公开(公告)号：US08872188B2

公开(公告)日：2014-10-28

申请号：US13501373

申请日：2010-01-19

申请人： Misako Honaga ,  Shin Harada

发明人： Misako Honaga ,  Shin Harada

IPC分类号： H01L29/12 ,  H01L29/78 ,  H01L21/3105 ,  H01L29/04 ,  H01L29/66 ,  H01L21/04 ,  H01L29/16 ,  H01L21/02 ,  H01L29/06

CPC分类号： H01L29/7802 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02609 ,  H01L21/049 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/78

摘要： A silicon carbide semiconductor device is provided that includes a semiconductor layer made of silicon carbide and having a surface tilted at an angle in a range of not less than 50° and not more than 65° relative to the {0001} plane, and an insulating film formed to contact the surface of the semiconductor layer. A maximum value of the nitrogen concentration in a region within 10 nm from the interface between the semiconductor layer and the insulating film is not less than 1×1021 cm−3, and the semiconductor device has a channel direction in a range of ±10° relative to the direction orthogonal to the direction in the surface of the semiconductor layer. A method of manufacturing the silicon carbide semiconductor device is also provided.

摘要翻译： 提供一种碳化硅半导体器件，其包括由碳化硅制成的半导体层，并且具有相对于{0001}面在不小于50°且不超过65°的范围内倾斜的表面，并且绝缘 形成为与半导体层的表面接触的膜。 半导体层与绝缘膜之间的界面10nm以内的氮浓度的最大值不小于1×1021cm-3，半导体器件的通道方向在±10°的范围内 相对于在半导体层的表面中与<-2110>方向正交的方向。 还提供了制造碳化硅半导体器件的方法。

公开(公告)号：US08686434B2

公开(公告)日：2014-04-01

申请号：US13063083

申请日：2009-02-03

申请人： Shin Harada ,  Takeyoshi Masuda ,  Keiji Wada ,  Masato Tsumori

发明人： Shin Harada ,  Takeyoshi Masuda ,  Keiji Wada ,  Masato Tsumori

IPC分类号： H01L29/06

CPC分类号： H01L29/1608 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/3003 ,  H01L21/324 ,  H01L29/045 ,  H01L29/0878 ,  H01L29/36 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/94

摘要： There is provided a silicon carbide semiconductor device having excellent electrical characteristics such as channel mobility, and a method for manufacturing the same. A semiconductor device includes a substrate made of silicon carbide and having an off-angle of greater than or equal to 50° and less than or equal to 65° with respect to a surface orientation of {0001}, a p-type layer serving as a semiconductor layer, and an oxide film serving as an insulating film. The p-type layer is formed on the substrate and is made of silicon carbide. The oxide film is formed to contact with a surface of the p-type layer. A maximum value of the concentration of nitrogen atoms in a region within 10 nm of an interface between the semiconductor layer and the insulating film (interface between a channel region and the oxide film) is greater than or equal to 1×1021 cm−3.

摘要翻译： 提供了具有优异的电特性如沟道迁移率的碳化硅半导体器件及其制造方法。 半导体器件包括相对于{0001}的表面取向具有大于或等于50°且小于或等于65°的偏角度的碳化硅制成的衬底，用作 半导体层和用作绝缘膜的氧化膜。 p型层形成在基板上，由碳化硅制成。 氧化膜形成为与p型层的表面接触。 半导体层与绝缘膜（沟道区域和氧化物膜之间的界面）的界面的10nm以内的区域的氮原子的浓度的最大值为1×1021cm-3以上。

公开(公告)号：US08643065B2

公开(公告)日：2014-02-04

申请号：US12919992

申请日：2009-12-11

申请人： Kazuhiro Fujikawa ,  Hideto Tamaso ,  Shin Harada ,  Yasuo Namikawa

发明人： Kazuhiro Fujikawa ,  Hideto Tamaso ,  Shin Harada ,  Yasuo Namikawa

IPC分类号： H01L29/80

CPC分类号： H01L29/66068 ,  H01L21/0465 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/8083

摘要： A JFET is a semiconductor device allowing more reliable implementation of the characteristics essentially achievable by employing SiC as a material and includes a wafer having at least an upper surface made of silicon carbide, and a gate contact electrode formed on the upper surface. The wafer includes a first p-type region serving as an ion implantation region formed so as to include the upper surface. The first p-type region includes a base region disposed so as to include the upper surface, and a protruding region. The base region has a width (w1) in the direction along the upper surface greater than a width (w2) of the protruding region. The gate contact electrode is disposed in contact with the first p-type region such that the gate contact electrode is entirely located on the first p-type region as seen in plan view.

摘要翻译： JFET是半导体器件，允许更可靠地实现通过使用SiC作为材料而基本上可实现的特性，并且包括至少由碳化硅制成的上表面的晶片和形成在上表面上的栅极接触电极。 晶片包括用作离子注入区域的第一p型区域，其形成为包括上表面。 第一p型区域包括设置成包括上表面的基极区域和突出区域。 基部区域沿着上表面的方向具有大于突出区域的宽度（w2）的宽度（w1）。 栅极接触电极设置成与第一p型区域接触，使得栅极接触电极完全位于第一p型区域上，如平面图所示。

公开(公告)号：US08536583B2

公开(公告)日：2013-09-17

申请号：US13063298

申请日：2010-03-23

申请人： Keiji Wada ,  Shin Harada ,  Takeyoshi Masuda ,  Misako Honaga

发明人： Keiji Wada ,  Shin Harada ,  Takeyoshi Masuda ,  Misako Honaga

IPC分类号： H01L29/15 ,  H01L31/0312

CPC分类号： H01L29/7802 ,  H01L29/045 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/94

摘要： A MOSFET includes: a silicon carbide (SiC) substrate having a main surface having an off angle of not less than 50° and not more than 65° relative to a {0001} plane; a semiconductor layer formed on the main surface of the SiC substrate; and an insulating film formed in contact with a surface of the semiconductor layer. The MOSFET has a sub-threshold slope of not more than 0.4 V/Decade.

摘要翻译： MOSFET包括：碳化硅（SiC）基板，其具有相对于{0001}面具有不小于50°且不大于65°的偏离角的主表面; 形成在所述SiC衬底的主表面上的半导体层; 以及与半导体层的表面接触形成的绝缘膜。 MOSFET的子阈值斜率不超过0.4 V /十年。

公开(公告)号：US08525187B2

公开(公告)日：2013-09-03

申请号：US13122353

申请日：2010-03-23

申请人： Shin Harada ,  Keiji Wada ,  Toru Hiyoshi

发明人： Shin Harada ,  Keiji Wada ,  Toru Hiyoshi

IPC分类号： H01L29/15

CPC分类号： H01L29/7395 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/78

摘要： An IGBT, which is capable of reducing on resistance by reducing channel mobility, includes: an n type substrate made of SiC and having a main surface with an off angle of not less than 50° and not more than 65° relative to a plane orientation of {0001}; a p type reverse breakdown voltage holding layer made of SiC and formed on the main surface of the substrate; an n type well region formed to include a second main surface of the reverse breakdown voltage holding layer; an emitter region formed in the well region to include the second main surface and including a p type impurity at a concentration higher than that of the reverse breakdown voltage holding layer; a gate oxide film formed on the reverse breakdown voltage holding layer; and a gate electrode formed on the gate oxide film. In a region including an interface between the well region and the gate oxide film, a high-concentration nitrogen region is formed to have a nitrogen concentration higher than those of the well region and the gate oxide film.

摘要翻译： 能够通过降低沟道迁移率而降低导通电阻的IGBT包括：由SiC制成的n型衬底，其主表面相对于平面取向具有不小于50度且不大于65度的偏离角 {0001}; 由SiC制成的p型反向击穿电压保持层，形成在基板的主表面上; 形成为包括反向击穿电压保持层的第二主表面的n型阱区; 在所述阱区域中形成的包括所述第二主表面并且包含浓度高于所述反向击穿电压保持层的p型杂质的发射极区域; 形成在反向击穿电压保持层上的栅极氧化膜; 以及形成在栅氧化膜上的栅电极。 在包括阱区和栅极氧化膜之间的界面的区域中，形成高浓度氮区，使得氮浓度高于阱区和栅极氧化膜的氮浓度。

公开(公告)号：US08502236B2

公开(公告)日：2013-08-06

申请号：US13122377

申请日：2010-03-23

申请人： Shin Harada ,  Keiji Wada ,  Toru Hiyoshi

发明人： Shin Harada ,  Keiji Wada ,  Toru Hiyoshi

IPC分类号： H01L29/15

CPC分类号： H01L29/7828 ,  H01L21/049 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/518 ,  H01L29/66068 ,  H01L29/7838 ,  H01L2924/0002 ,  H01L2924/00

摘要： A MOSFET, which is capable of reducing on resistance by reducing channel mobility even when a gate voltage is high, includes: an n type substrate made of SiC and having a main surface with an off angle of 50°-65° relative to a {0001} plane; an n type reverse breakdown voltage holding layer made of SiC and formed on the main surface of the substrate; a p type well region formed in the reverse breakdown voltage holding layer distant away from a first main surface thereof; a gate oxide film formed on the well region; an n type contact region disposed between the well region and the gate oxide film; a channel region connecting the n type contact region and the reverse breakdown voltage holding layer; and a gate electrode disposed on the gate oxide film. In a region including an interface between the channel region and the gate oxide film, a high-concentration nitrogen region is formed.

摘要翻译： 即使栅极电压高，通过降低沟道迁移能力也能够降低导通电阻的MOSFET包括：由SiC制成的n型衬底，其主表面相对于{ 0001}平面; 由SiC制成的n型反向击穿电压保持层，形成在基板的主表面上; 形成在远离其第一主表面的反向击穿电压保持层中的p型阱区; 形成在所述阱区上的栅氧化膜; 设置在所述阱区域和所述栅氧化膜之间的n型接触区域; 连接n型接触区域和反向击穿电压保持层的沟道区域; 以及设置在栅氧化膜上的栅电极。 在包括沟道区域和栅极氧化膜之间的界面的区域中，形成高浓度氮区域。

公开(公告)号：US08450750B2

公开(公告)日：2013-05-28

申请号：US13130986

申请日：2010-01-27

申请人： Misako Honaga ,  Shin Harada

发明人： Misako Honaga ,  Shin Harada

IPC分类号： H01L29/15

CPC分类号： H01L21/28008 ,  H01L21/049 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/518 ,  H01L29/66068 ,  H01L29/7813

摘要： A silicon carbide semiconductor device is provided that includes a semiconductor layer made of silicon carbide and having a surface with a trench having a sidewall formed of a crystal plane tilted at an angle in a range of not less than 50° and not more than 65° relative to the {0001} plane, and an insulating film formed to contact the sidewall of the trench. A maximum value of the nitrogen concentration in a region within 10 nm from the interface between the sidewall of the trench and the insulating film is not less than 1×1021 cm−3, and the semiconductor device has a channel direction in a range of ±10° relative to the direction orthogonal to the direction in the sidewall of the trench. A method of manufacturing the silicon carbide semiconductor device is also provided.

摘要翻译： 提供一种碳化硅半导体器件，其包括由碳化硅制成的半导体层，并具有具有沟槽的表面，所述沟槽具有由以不小于50°且不大于65°的范围内倾斜的晶体面形成的侧壁 相对于{0001}面，以及形成为与沟槽的侧壁接触的绝缘膜。 与沟槽侧壁和绝缘膜之间的界面10nm以内的区域的氮浓度的最大值不小于1×1021cm-3，半导体器件的沟道方向在± 相对于沟槽侧壁中与<-2110>方向垂直的方向为10°。 还提供了制造碳化硅半导体器件的方法。