公开(公告)号：US07355897B2

公开(公告)日：2008-04-08

申请号：US11773857

申请日：2007-07-05

申请人： Tzu-Hsuan Hsu ,  Yen-Hao Shih

发明人： Tzu-Hsuan Hsu ,  Yen-Hao Shih

IPC分类号： G11C16/04

CPC分类号： G11C16/0475

摘要： A method for operating a nitride trapping memory cell is provided to resolve hard-to-erase condition by employing a reset technique to eliminate or reduce the number of electrons in the middle of a junction region. When a hard-to-erase condition is detected after a series of program and erase cycles, such as 500 or 100 program and erase cycles, a substrate transient hot hole (STHH) reset operation is applied. The substrate transient hot hole reset injects holes that are far away junction than band-to-band tunneling hot hole (BTBTHH) injection such that the STHH reset on cycle endurance is able to maintain a desirable cycle window to eliminate or reduce the hard-to erase condition in subsequent program and erase cycles.

摘要翻译： 提供了一种操作氮化物捕获存储单元的方法，通过采用复位技术来消除或减少接合区中间的电子数量来解决硬擦除条件。 当在一系列编程和擦除周期（例如500或100个编程和擦除周期）之后检测到难以擦除的条件时，应用基板瞬态热孔（STHH）复位操作。 衬底瞬态热孔复位注入与带 - 带隧道热孔（BTBTHH）注入相距较远的结的孔，使得周期耐久下的STHH复位能够保持期望的循环窗口以消除或减少难以 随后的编程和擦除周期中的擦除条件。

公开(公告)号：US20080002477A1

公开(公告)日：2008-01-03

申请号：US11836142

申请日：2007-08-09

申请人： Tzu-Hsuan Hsu ,  Erh-Kun Lai ,  Hang-Ting Lue ,  Chia-Hua Ho

发明人： Tzu-Hsuan Hsu ,  Erh-Kun Lai ,  Hang-Ting Lue ,  Chia-Hua Ho

IPC分类号： G11C11/34 ,  H01L21/36

CPC分类号： H01L29/7923 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/42352

摘要： The invention is directed to a memory cell on a substrate having a plurality of shallow trench isolations form therein, wherein top surfaces of the shallow trench isolations are lower than a top surface of the substrate and the shallow trench isolations together define a vertical fin structure of the substrate. The memory comprises a straddle gate, a carrier trapping layer and at least two source/drain regions. The straddle gate is located on the substrate and straddles over the vertical fin structure. The carrier trapping layer is located between the straddle gate and the substrate. The source/drain regions are located in a portion of the vertical fin structure of the substrate exposed by the straddle gate.

摘要翻译： 本发明涉及在其上形成有多个浅沟槽隔离物的衬底上的存储单元，其中浅沟槽隔离物的顶表面低于衬底的顶表面，并且浅沟槽隔离件一起限定垂直鳍状结构 底物。 存储器包括跨骑门，载体俘获层和至少两个源极/漏极区域。 跨门位于基板上，跨越垂直翅片结构。 载体捕获层位于跨门和基板之间。 源极/漏极区域位于由跨门暴露的衬底的垂直鳍结构的一部分中。

公开(公告)号：US07242622B2

公开(公告)日：2007-07-10

申请号：US11359044

申请日：2006-02-22

申请人： Tzu-Hsuan Hsu ,  Yen-Hao Shih

发明人： Tzu-Hsuan Hsu ,  Yen-Hao Shih

IPC分类号： G11C16/04

CPC分类号： G11C16/0475

摘要： A method for operating a nitride trapping memory cell is provided to resolve hard-to-erase condition by employing a reset technique to eliminate or reduce the number of electrons in the middle of a junction region. When a hard-to-erase condition is detected after a series of program and erase cycles, such as 500 or 100 program and erase cycles, a substrate transient hot hole (STHH) reset operation is applied. The substrate transient hot hole reset injects holes that are far away junction than band-to-band tunneling hot hole (BTBTHH) injection such that the STHH reset on cycle endurance is able to maintain a desirable cycle window to eliminate or reduce the hard-to erase condition in subsequent program and erase cycles.

摘要翻译： 提供了一种操作氮化物捕获存储单元的方法，通过采用复位技术来消除或减少接合区中间的电子数量来解决硬擦除条件。 当在一系列编程和擦除周期（例如500或100个编程和擦除周期）之后检测到难以擦除的条件时，应用基板瞬态热孔（STHH）复位操作。 衬底瞬态热孔复位注入与带 - 带隧道热孔（BTBTHH）注入相距较远的结的孔，使得周期耐久下的STHH复位能够保持期望的循环窗口以消除或减少难以 随后的编程和擦除周期中的擦除条件。

公开(公告)号：US20070133307A1

公开(公告)日：2007-06-14

申请号：US11359044

申请日：2006-02-22

申请人： Tzu-Hsuan Hsu ,  Yen-Hao Shih

发明人： Tzu-Hsuan Hsu ,  Yen-Hao Shih

IPC分类号： G11C16/04

CPC分类号： G11C16/0475

摘要： A method for operating a nitride trapping memory cell is provided to resolve hard-to-erase condition by employing a reset technique to eliminate or reduce the number of electrons in the middle of a junction region. When a hard-to-erase condition is detected after a series of program and erase cycles, such as 500 or 100 program and erase cycles, a substrate transient hot hole (STHH) reset operation is applied. The substrate transient hot hole reset injects holes that are far away junction than band-to-band tunneling hot hole (BTBTHH) injection such that the STHH reset on cycle endurance is able to maintain a desirable cycle window to eliminate or reduce the hard-to erase condition in subsequent program and erase cycles.

公开(公告)号：US20060131634A1

公开(公告)日：2006-06-22

申请号：US10905194

申请日：2004-12-21

申请人： Tzu-Hsuan Hsu ,  Yen-Hao Shih

发明人： Tzu-Hsuan Hsu ,  Yen-Hao Shih

IPC分类号： H01L21/8238 ,  H01L29/06

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/792

摘要： A non-volatile memory cell comprising a substrate, a charge-trapping layer, a control gate, a first conductive state of source and drain, a lightly doped region and a second conductive state of pocket-doped region. The charge-trapping layer and the control gate are disposed over the substrate. A dielectric layer is disposed between the substrate, the charge-trapping layer and the control gate. The source and drain are disposed in the substrate on each side of the charge-trapping layer. The lightly doped region is disposed on the substrate surface between the source and the charge-trapping layer. The pocket-doped region is disposed within the substrate between the drain and the charge-trapping layer. Because there are asymmetrical configuration and different doped conductive states of implant structures, the programming speed of the memory cell is increased, the neighboring cell disturb issue is prevented, and the area occupation of the bit line selection transistor is reduced.

摘要翻译： 一种非易失性存储单元，包括衬底，电荷俘获层，控制栅极，源极和漏极的第一导电状态，轻掺杂区域和第二导电状态的袋掺杂区域。 电荷捕获层和控制栅极设置在衬底上。 电介质层设置在基板，电荷俘获层和控制栅极之间。 源极和漏极设置在电荷俘获层的每一侧上的衬底中。 轻掺杂区域设置在源极和电荷捕获层之间的衬底表面上。 掺杂阱区域设置在漏极和电荷捕获层之间的衬底内。 由于存在不对称配置和掺杂导体状态的不同，存储单元的编程速度增加，从而防止了相邻单元的干扰问题，并减少了位线选择晶体管的占用面积。

公开(公告)号：US20050124116A1

公开(公告)日：2005-06-09

申请号：US10728767

申请日：2003-12-08

申请人： Tzu-Hsuan Hsu ,  Ming-Hsiu Lee ,  Hsiang-Lan Lung ,  Chao-I Wu

发明人： Tzu-Hsuan Hsu ,  Ming-Hsiu Lee ,  Hsiang-Lan Lung ,  Chao-I Wu

IPC分类号： H01L21/336 ,  H01L27/06 ,  H01L31/113

CPC分类号： H01L27/0688

摘要： A 3D polysilicon read only memory at least including: a silicon substrate, an isolated silicon dioxide (SiO2) layer, a N-Type heavily doped (N+) polysilicon layer, a first oxide layer, a dielectric layer, a P-Type lightly doped (P−) polysilicon layer, at least a neck structure, and a second oxide layer. The isolated SiO2 layer is deposited on the silicon substrate, and the N+ polysilicon layer is deposited on the isolated SiO2 layer. The N+ polysilicon layer is further defined a plurality of parallel, separate word lines (WL), and the first oxide layer is filled in the space between the word lines. The dielectric layer is deposited on the word lines and the first oxide layer. The P-Type lightly doped (P−) polysilicon layer is deposited on the dielectric layer and is further defined a plurality of parallel, separate bit lines (BL). The bit lines overlap the word lines, from a top view, to form a shape approximately as a cross. There are at least a neck structure individually formed between the first polysilicon layer and the second polysilicon layer by isotropy wet etching the dielectric layer, with using dilute hydrofluoric acid (HF) as the example. The second oxide layer is filled in the space between the bit lines and is on the word lines and the first oxide layer.

摘要翻译： 至少包括硅衬底，隔离二氧化硅（SiO 2）层，N型重掺杂（N +）多晶硅层，第一氧化物层，电介质 层，P型轻掺杂（P）多晶硅层，至少颈部结构和第二氧化物层。 隔离的SiO 2层沉积在硅衬底上，并且N +多晶硅层沉积在隔离的SiO 2层上。 N +多晶硅层进一步限定多个平行的单独的字线（WL），并且第一氧化物层被填充在字线之间的空间中。 介电层沉积在字线和第一氧化物层上。 P型轻掺杂（P）多晶硅层沉积在电介质层上，并进一步限定多个平行的分开的位线（BL）。 位线从顶视图与字线重叠，以形成大致为十字形的形状。 通过使用稀氢氟酸（HF）作为实例，通过各向同性湿蚀刻介电层，至少在第一多晶硅层和第二多晶硅层之间形成颈部结构。 第二氧化物层填充在位线之间的空间中，并且位于字线和第一氧化物层上。

公开(公告)号：US08975687B2

公开(公告)日：2015-03-10

申请号：US12813906

申请日：2010-06-11

申请人： Hang-Ting Lue ,  Tzu-Hsuan Hsu ,  Sheng-Chih Lai

发明人： Hang-Ting Lue ,  Tzu-Hsuan Hsu ,  Sheng-Chih Lai

IPC分类号： H01L29/76 ,  H01L29/792 ,  G11C16/04 ,  H01L21/28 ,  H01L27/115 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L21/265

CPC分类号： H01L29/792 ,  G11C16/0483 ,  H01L21/26513 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833

摘要： An integrated circuit of an array of nonvolatile memory cells has a dielectric stack layer over the substrate, and implanted regions in the substrate under the dielectric stack layer. The dielectric stack layer is continuous over a planar region, that includes locations of the dielectric stack layer that store nonvolatile data, such that these locations are accessed by word lines/bit lines.

摘要翻译： 非易失性存储单元阵列的集成电路在衬底上具有介电堆叠层，并且在介电堆叠层下方的衬底中的注入区域。 电介质堆叠层在平面区域上是连续的，其包括存储非易失性数据的电介质堆叠层的位置，使得这些位置被字线/位线访问。

公开(公告)号：US08847299B2

公开(公告)日：2014-09-30

申请号：US12017064

申请日：2008-01-21

申请人： Tzu-Hsuan Hsu ,  Yen-Hao Shih

发明人： Tzu-Hsuan Hsu ,  Yen-Hao Shih

IPC分类号： H01L29/76 ,  H01L27/115 ,  H01L29/792

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/792

摘要： A non-volatile memory cell comprising a substrate, a charge-trapping layer, a control gate, a first conductive state of source and drain, a lightly doped region and a second conductive state of pocket-doped region. The charge-trapping layer and the control gate are disposed over the substrate. A dielectric layer is disposed between the substrate, the charge-trapping layer and the control gate. The source and drain are disposed in the substrate on each side of the charge-trapping layer. The lightly doped region is disposed on the substrate surface between the source and the charge-trapping layer. The pocket-doped region is disposed within the substrate between the drain and the charge-trapping layer. Because there are asymmetrical configuration and different doped conductive states of implant structures, the programming speed of the memory cell is increased, the neighboring cell disturb issue is prevented, and the area occupation of the bit line selection transistor is reduced.

摘要翻译： 一种非易失性存储单元，包括衬底，电荷俘获层，控制栅极，源极和漏极的第一导电状态，轻掺杂区域和第二导电状态的袋掺杂区域。 电荷捕获层和控制栅极设置在衬底上。 电介质层设置在基板，电荷俘获层和控制栅极之间。 源极和漏极设置在电荷俘获层的每一侧上的衬底中。 轻掺杂区域设置在源极和电荷捕获层之间的衬底表面上。 掺杂阱区域设置在漏极和电荷捕获层之间的衬底内。 由于存在不对称配置和掺杂导体状态的不同，存储单元的编程速度增加，从而防止了相邻单元的干扰问题，并减少了位线选择晶体管的占用面积。

公开(公告)号：US08325530B2

公开(公告)日：2012-12-04

申请号：US11542749

申请日：2006-10-03

申请人： Hang-Ting Lue ,  Tzu-Hsuan Hsu ,  Erh-Kun Lai

发明人： Hang-Ting Lue ,  Tzu-Hsuan Hsu ,  Erh-Kun Lai

IPC分类号： G11C11/34

CPC分类号： G11C16/10 ,  G11C16/0416 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/7851 ,  H01L29/7883

摘要： A method of performing an operation on a flash memory cell device, used when a gate coupling ratio between a floating gate and a control gate of less than 0.4. A potential is required to be applied across the control gate. Electrons are either injected to the floating gate from the control gate or ejected from the floating gate to the control gate. The operation associated with the injection or the ejection is determined by the nature of a silicon channel provided in the device. Devices using a bulk-tied FinFET-like structure are particularly suited to this method. The method is also particularly suited for use on cells in a NAND array.

摘要翻译： 在浮动栅极和控制栅极之间的栅极耦合比小于0.4时使用的对闪存单元器件进行操作的方法。 需要在控制门上施加电位。 电子从控制栅极注入到浮动栅极或从浮动栅极喷射到控制栅极。 与注射或喷射相关联的操作由设备中提供的硅通道的性质决定。 使用大容量FinFET类结构的器件特别适用于该方法。 该方法还特别适用于NAND阵列中的单元。

公开(公告)号：US20110115048A1

公开(公告)日：2011-05-19

申请号：US13009354

申请日：2011-01-19

申请人： Ching-Chun Wang ,  Tzu-Hsuan Hsu

发明人： Ching-Chun Wang ,  Tzu-Hsuan Hsu

IPC分类号： H01L29/06 ,  H01L23/58

CPC分类号： H01L23/522 ,  H01L21/6836 ,  H01L21/76256 ,  H01L21/76898 ,  H01L23/53223 ,  H01L23/53238 ,  H01L2221/6834 ,  H01L2924/0002 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00

摘要： Provided is a method of fabricating a semiconductor device that includes providing a semiconductor substrate having a front side and a back side, forming a first circuit and a second circuit at the front side of the semiconductor substrate, bonding the front side of the semiconductor substrate to a carrier substrate, thinning the semiconductor substrate from the back side, and forming an trench from the back side to the front side of the semiconductor substrate to isolate the first circuit from the second circuit.

摘要翻译： 提供一种制造半导体器件的方法，该半导体器件包括提供具有正面和背面的半导体衬底，在半导体衬底的正面形成第一电路和第二电路，将半导体衬底的正面粘合到 载体衬底，从背面减薄半导体衬底，并且从半导体衬底的背侧到前侧形成沟槽，以将第一电路与第二电路隔离。