公开(公告)号：US06914549B2

公开(公告)日：2005-07-05

申请号：US10661861

申请日：2003-09-12

申请人： Feng Chen ,  Ranjit Gharpurey

发明人： Feng Chen ,  Ranjit Gharpurey

IPC分类号： H03M1/00 ,  H03M1/12 ,  H03M1/16 ,  H03M3/00 ,  H03M3/04

CPC分类号： H03M1/005 ,  H03M1/167 ,  H03M3/398 ,  H03M3/416

摘要： Configuring an analog-to-digital converter includes receiving a control signal and an input analog signal at an analog-to-digital converter, where the control signal has either a first state or a second state. The first state is associated with a first configuration and the second state is associated with a second configuration. If the control signal has the first state, the analog-to-digital-converter is configured in the first configuration and a digital signal comprising a first digital signal is generated according to a pipeline conversion. If the control signal has the second state the analog-to-digital converter is configured in the second configuration and the digital signal comprising a second digital signal is generated according to a multi-stage sigma delta modulation conversion. The digital signal is processed to yield a digital output.

摘要翻译： 配置模数转换器包括在模拟 - 数字转换器处接收控制信号和输入模拟信号，其中控制信号具有第一状态或第二状态。 第一状态与第一配置相关联，并且第二状态与第二配置相关联。 如果控制信号具有第一状态，则在第一配置中配置模数转换器，并且根据流水线转换产生包括第一数字信号的数字信号。 如果控制信号具有第二状态，则在第二配置中配置模数转换器，并且根据多级Σ-Δ调制转换产生包括第二数字信号的数字信号。 数字信号被处理以产生数字输出。

公开(公告)号：US06906108B2

公开(公告)日：2005-06-14

申请号：US09932555

申请日：2001-08-17

申请人： Gregg Henderson ,  Donald O. Heumann ,  Roger A. Laine ,  Lara Maistrello ,  Betty C. R. Zhu ,  Feng Chen

发明人： Gregg Henderson ,  Donald O. Heumann ,  Roger A. Laine ,  Lara Maistrello ,  Betty C. R. Zhu ,  Feng Chen

IPC分类号： A01N31/04 ,  A01N35/06 ,  A01N45/02 ,  A01N65/00 ,  A61K31/12 ,  A61K31/045 ,  A61K31/015 ,  A01N27/00

CPC分类号： A01N31/04 ,  A01N35/06 ,  A01N45/02 ,  A01N65/06 ,  A01N65/44 ,  Y02A50/322

摘要： Extracts of vetiver oil were found to be significant repellents and toxicants of ants, ticks, and cockroaches. Nootkatone was shown to significantly decrease ant invasion and increase mortality in fire ants. Nootkatone is an effective repellent and toxicant of ants either by itself or as an addition to other substrates, including mulches made from vetiver grass roots, diatomaceous earth, alumina, silica, clays; building materials made from either aluminum or wood; and other suitable solid substances. Nootkatone was also a repellent and toxicant to ticks; and a repellent to cockroaches. Nootkatone is non-toxic to humans and other mammals and is environmentally safe. In addition, it is believed that other extracts of vetiver oil, specifically α-cedrene, zizanol and bicyclovetivenol, will be effective against ants, ticks, and cockroaches.

摘要翻译： 发现香根草油的提取物是蚂蚁，蜱和蟑螂的驱虫剂和有毒物质。 Nootkatone被证明可以显着降低蚂蚁入侵并增加蚂蚁的死亡率。 Nootkatone是本身或作为其他底物的补充剂，包括由香根草草根，硅藻土，氧化铝，二氧化硅，粘土制成的覆盖物的有效驱避剂和毒物; 铝或木制建筑材料; 和其他合适的固体物质。 Nootkatone也是蜱虫的驱避剂和毒物; 和驱虫剂蟑螂。 Nootkatone对人类和其他哺乳动物无毒，对环境无害。 此外，据信香根草油的其他提取物，特别是α-雪松烯，齐赞醇和双环己酮醇，对蚂蚁，蜱和蟑螂有效。

公开(公告)号：US20050113002A1

公开(公告)日：2005-05-26

申请号：US10720409

申请日：2003-11-24

申请人： Feng Chen ,  Cing Lim ,  Lup Leong ,  Sim Wang

发明人： Feng Chen ,  Cing Lim ,  Lup Leong ,  Sim Wang

IPC分类号： B24B37/04 ,  B24B1/00

CPC分类号： B24B37/32

摘要： A chemical-mechanical polish (CMP) machine and fabrication process using the same. The CMP machine has a CMP retaining ring comprising: an inner peripheral surface; an outer peripheral surface; a lower surface adapted to contact and depress an upper surface of a polishing pad during chemical mechanical polishing of a lower surface of a substrate. The substrate is contained within the inner peripheral surface of the retaining ring during chemical mechanical polishing. At least a groove on the lower surface of the retaining ring. At least a portion of the groove has a rounded contour. In an aspect, the groove has a semicircle profile. In another aspect, the groove has a semicircle profile and a curved top corner profile at adjacent to the lower surface of the retaining ring. The retaining ring with a curved portion of groove reduces the accumulation of dried slurry in the groove and thus reduces micro-scratches.

摘要翻译： 化学机械抛光（CMP）机器及其制造工艺。 CMP机器具有CMP保持环，其包括：内周面; 外周面; 适于在衬底的下表面的化学机械抛光期间接触和压下抛光垫的上表面的下表面。 在化学机械抛光期间，基板被包含在保持环的内周表面内。 至少在保持环的下表面上的凹槽。 凹槽的至少一部分具有圆形轮廓。 在一方面，凹槽具有半圆形轮廓。 在另一方面，凹槽具有与保持环的下表面相邻的半圆形轮廓和弯曲的顶角轮廓。 具有凹槽的弯曲部分的保持环减少了干燥的浆料在凹槽中的积聚，从而减少微划痕。

公开(公告)号：US20050110664A1

公开(公告)日：2005-05-26

申请号：US10723472

申请日：2003-11-26

申请人： Feng Chen

发明人： Feng Chen

IPC分类号： H03M1/06 ,  H03M1/66 ,  H03M3/00

CPC分类号： H03M1/0663 ,  H03M3/464

摘要： A digital-to-analog converter (DAC) error suppression arrangement suppresses DAC error arising from mismatched elements contained in a DAC (640 and/or 645) that is part of a modulator (FIG. 6). A low pass averaging (LPA) index decoder 650 controls a shifting arrangement 635 to shift a digital word T2 derived from modulator output Y so that the DAC error distribution constitutes a low pass profile (FIG. 5). Thus, DAC error is suppressed at higher frequencies (close to half the sampling rate), thereby providing improved spurious free dynamic range (SFDR). The LPA index decoder 650 causes the shifting arrangement 635 to shift the digital word T2 using only a single pointer per clock cycle.

摘要翻译： 数模转换器（DAC）误差抑制装置抑制由作为调制器（图6）的一部分的DAC（640和/或645）中包含的不匹配元件引起的DAC误差。 低通平均（LPA）索引解码器650控制移位装置635以移位从调制器输出Y导出的数字字T 2，使得DAC误差分布构成低通廓线（图5）。 因此，在较高频率（接近采样速率的一半）时DAC误差被抑制，从而提供改善的无杂散动态范围（SFDR）。 LPA索引解码器650使移位装置635在每个时钟周期仅使用单个指针来移位数字字T 2。

公开(公告)号：US06697896B1

公开(公告)日：2004-02-24

申请号：US09476614

申请日：1999-12-31

申请人： Feng Chen

发明人： Feng Chen

IPC分类号： G06F1300

CPC分类号： G06F13/4072 ,  Y02D10/14 ,  Y02D10/151

摘要： A device contains a first device and a second device. In one embodiment, the first device drives at least three signals, a first reference signal, and a second reference signal. The second device, which is coupled to the first device, receives the at least three signals, the first reference signal, and the second reference signal. The second device identifies values for the at least three signals according to the first reference signal and the second reference signal.

摘要翻译： 设备包含第一设备和第二设备。 在一个实施例中，第一设备驱动至少三个信号，第一参考信号和第二参考信号。 耦合到第一装置的第二装置接收至少三个信号，第一参考信号和第二参考信号。 第二装置根据第一参考信号和第二参考信号识别至少三个信号的值。

公开(公告)号：US06697003B1

公开(公告)日：2004-02-24

申请号：US10417616

申请日：2003-04-17

申请人： Feng Chen

发明人： Feng Chen

IPC分类号： H03M300

CPC分类号： H03M1/066 ,  H03M1/0617 ,  H03M3/464

摘要： Dynamic element matching systems and methods are provided in which a current dynamic element matching code is generated according to a previous dynamic element matching code, a digital input code, and a dither code. The current dynamic element matching code is then used along with the digital input code to select digital to analog converter elements.

摘要翻译： 提供了动态元素匹配系统和方法，其中根据先前的动态元素匹配代码，数字输入代码和抖动代码生成当前动态元素匹配代码。 然后将当前的动态元件匹配代码与数字输入代码一起使用以选择数模转换器元件。

公开(公告)号：US06528886B2

公开(公告)日：2003-03-04

申请号：US10135330

申请日：2002-04-29

申请人： Huang Liu ,  John Sudijono ,  Juan Boon Tan ,  Edwin Goh ,  Alan Cuthbertson ,  Arthur Ang ,  Feng Chen ,  Qiong Li ,  Peter Chew

发明人： Huang Liu ,  John Sudijono ,  Juan Boon Tan ,  Edwin Goh ,  Alan Cuthbertson ,  Arthur Ang ,  Feng Chen ,  Qiong Li ,  Peter Chew

IPC分类号： H01L2348

CPC分类号： H01L21/76826 ,  H01L21/31612 ,  H01L21/31629 ,  H01L21/76831

摘要： An intermetal dielectric structure for integrated circuits is provided having a premetal dielectric and a metal line thereon, with a SRO liner on the premetal dielectric layer and the metal lines, a FGS dielectric layer over the SRO liner, a SRO film over the FGS dielectric layer, and a TEOS dielectric layer over the SRO film. Vias through the FGS dielectric layer are treated to have fluorine-free regions around the vias. The structure is not subject to fluorine attack on the metal lines or vias while having a stable FGS dielectric layer with less fluorine out-gassing and out-diffusion.

摘要翻译： 提供了一种用于集成电路的金属间电介质结构，其上具有前金属电介质和金属线，在前金属介电层和金属线上具有SRO衬垫，在SRO衬垫上的FGS电介质层，在FGS介电层上的SRO膜 ，以及SRO膜上的TEOS电介质层。 通过FGS介电层的通孔被处理成在通孔周围具有无氟区域。 该结构不会对金属线或通孔发生氟侵蚀，同时具有较少氟排出和扩散的稳定的FGS介电层。

公开(公告)号：US06433711B1

公开(公告)日：2002-08-13

申请号：US09711349

申请日：2000-11-09

申请人： Feng Chen

发明人： Feng Chen

IPC分类号： H03M106

CPC分类号： H03K5/24 ,  H03F3/45968 ,  H03F2200/331

摘要： An offset error compensation system is provided that includes a comparator (42) having an offset error (44), a positive receptor (56), a negative receptor (58), a positive output (60), and a negative output (62). A sequence generator (14) generates control signals (22) representing normal cycles and swap cycles. A first cross connect (46) is coupled to the positive receptor (56), the negative receptor (58), a positive input signal (52), and a negative input signal (54). The first cross connect (46) couples the positive input signal (52) to the positive receptor (56) and the negative input signal (54) to the negative receptor (58) in response to a normal cycle. The first cross connect (46) further couples the positive input signal (52) to the negative receptor (58) and the negative input signal (54) to the positive receptor (56) in response to a swap cycle. A second cross connect (48) is coupled to the positive receptor (56), the negative receptor (58), the positive output (60), and the negative output (62). The second cross connect (48) couples the positive receptor (56) to the positive output (60) and the negative receptor (58) to the negative output (62) in response to the normal cycle. The second cross connect (48) further couples the positive receptor (56) to the negative output (62) and the negative receptor (58) to the positive output (60) in response the swap cycle.

摘要翻译： 提供了一种偏移误差补偿系统，其包括具有偏移误差（44），正接收器（56），负接收器（58），正输出（60）和负输出（62）的比较器（42） 。 序列发生器（14）产生表示正常周期和交换周期的控制信号（22）。 第一交叉连接（46）耦合到正接收器（56），负接收器（58），正输入信号（52）和负输入信号（54）。 第一交叉连接（46）响应于正常周期将正输入信号（52）耦合到正接收器（56）和负输入信号（54）耦合到负接收器（58）。 响应于交换周期，第一交叉连接（46）还将正输入信号（52）与负接收器（58）和负输入信号（54）耦合到正接收器（56）。 第二交叉连接器（48）耦合到正接收器（56），负接收器（58），正输出端（60）和负输出端（62）。 第二交叉连接器（48）响应于正常周期将正接收器（56）耦合到正输出（60）和负接收器（58）耦合到负输出端（62）。 响应于交换周期，第二交叉连接器（48）还将正接收器（56）与负输出端（62）和负接收器（58）耦合到正输出端（60）。

公开(公告)号：US06376378B1

公开(公告)日：2002-04-23

申请号：US09415364

申请日：1999-10-08

申请人： Feng Chen ,  Lup San Leong ,  Charles Lin

发明人： Feng Chen ,  Lup San Leong ,  Charles Lin

IPC分类号： H01L21461

CPC分类号： B24B37/042 ,  B24B37/20 ,  H01L21/31053 ,  H01L21/3212

摘要： In one embodiment, a dielectric layer (144, 156) overlying a semiconductor substrate (28) is uniformly polished. During polishing, the perimeter (32) of the semiconductor substrate (28) overlies a peripheral region (16, 48, 66, 86, 120) of a polishing pad (6, 42, 60, 80, 100) and an edge portion (36) of the front surface of semiconductor substrate (28) is not in contact with the front surface (18, 50, 68, 88, 122) of the polishing pad (6, 42, 60, 80, 100), in the peripheral region (16, 48, 66, 86, 120). As a result, the polishing rate at the edge portion (36) of the semiconductor substrate (28) is reduced, and the semiconductor substrate (28) is polished with improved center to edge uniformity. Since the semiconductor substrate (28) is polished with improved center to edge uniformity, die yield is increased because die located within the edge portion (36) of the semiconductor substrate (28) are not over polished.

摘要翻译： 在一个实施例中，覆盖半导体衬底（28）的电介质层（144,156）被均匀抛光。 在抛光期间，半导体衬底（28）的周边（32）覆盖在抛光垫（6,42,60,80,100）和边缘部分（16,48,66,101）周边区域 半导体衬底（28）的前表面的表面（36）不与抛光垫（6,42,60,80,100）的前表面（18,50,68,88,100）接触， 区域（16,48,66,86,120）。 结果，半导体衬底（28）的边缘部分（36）处的抛光速率降低，并且半导体衬底（28）以改善的中心到边缘均匀性被抛光。 由于半导体基板（28）以改善的中心到边缘均匀性被抛光，所以由于位于半导体基板（28）的边缘部分（36）内的模具没有被过度抛光，所以提高了模具的产量。

公开(公告)号：US06284644B1

公开(公告)日：2001-09-04

申请号：US09684518

申请日：2000-10-10

申请人： Arthur Khoon Siah Aug ,  Feng Chen ,  Qiong Li

发明人： Arthur Khoon Siah Aug ,  Feng Chen ,  Qiong Li

IPC分类号： H01L214763

CPC分类号： H01L21/76829 ,  G01V3/15 ,  H01L21/76801 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76831

摘要： A method of forming a metal interconnect within a fluorinated silica glass dielectric layer while preventing outgassing from the FSG dielectric layer, comprising the following steps. A semiconductor structure having a metal structure, with an overlying liner layer, formed thereover is provided. A FSG dielectric layer is formed over the liner layer. The FSG dielectric layer having an exposed upper surface. The FSG dielectric layer is treated with a first nitrogen gas/plasma treatment to form a fluorine depleted upper capping layer from the exposed surface of the FSG dielectric layer. A TEOS oxide layer is formed over the upper capping layer. The TEOS oxide layer is planarized to form a planarized TEOS oxide layer. The planarized TEOS oxide layer, the upper capping layer, the treated FSG dielectric layer, and the liner layer are patterned to form a via hole therethrough, exposing a portion of the metal structure and exposing sidewalls of the patterned treated FSG dielectric layer within the via opening. At least the exposed sidewalls of the patterned treated fluorinated silicon glass dielectric layer within the via opening is treated with a second nitrogen gas/plasma treatment to form a fluorine depleted sidewall capping layer from the exposed sidewalls of the patterned treated fluorinated silicon glass dielectric layer, wherein the upper and sidewall capping layers prevent the outgassing from the patterned FSG dielectric layer. A metal interconnect is formed within the via opening.

摘要翻译： 一种在氟化石英玻璃介电层内形成金属互连的方法，同时防止从FSG介电层脱气，包括以下步骤。 提供具有金属结构的半导体结构，其上形成有覆盖衬垫层。 FSG电介质层形成在衬层上。 FSG电介质层具有暴露的上表面。 用第一氮气/等离子体处理处理FSG电介质层，以从FSG电介质层的暴露表面形成耗尽氟的上覆盖层。 在上盖层上形成TEOS氧化物层。 将TEOS氧化物层平坦化以形成平坦化的TEOS氧化物层。 对平坦化的TEOS氧化物层，上覆盖层，经处理的FSG电介质层和衬里层进行图案化以形成穿过其中的通孔，暴露金属结构的一部分并暴露图案化处理的FSG介电层的侧壁在通孔内 开放 通过第二氮气/等离子体处理处理至少通孔开口内图案化处理的氟化硅玻璃介电层的暴露的侧壁，以从图案化处理的氟化硅玻璃介电层的暴露的侧壁形成氟耗尽的侧壁封盖层， 其中上侧壁封盖层和侧壁封盖层防止从图案化的FSG电介质层脱气。 在通孔开口内形成金属互连。