公开(公告)号：US20120139054A1

公开(公告)日：2012-06-07

申请号：US13108742

申请日：2011-05-16

申请人： Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

发明人： Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

IPC分类号： H01L27/092 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78

CPC分类号： H01L29/4983 ,  H01L21/28114 ,  H01L21/32137 ,  H01L21/823807 ,  H01L21/82385 ,  H01L21/823864 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7845

摘要： The present invention relates to a device having adjustable channel stress and method thereof. There is provided an MOS device (200, 300), comprising a semiconductor substrate (202, 302); a channel formed on the semiconductor substrate (202, 302); a gate dielectric layer (204, 304) formed on the channel; a gate conductor (206, 306) formed on the gate dielectric layer (204, 304); and a source and a drain formed on both sides of the gate; wherein the gate conductor (206, 306) has a shape for producing a first stress to be applied to the channel so as to adjust the mobility of carriers in the channel. In the present invention, the shape of the gate conductor may be adjusted by controlling the etching process parameter, thus the stress in the channel may be adjusted conveniently, meanwhile, it may be used in combination with other mechanisms that generate stresses to obtain the desired channel stress.

摘要翻译： 本发明涉及具有可调节通道应力的装置及其方法。 提供一种包括半导体衬底（202,302）的MOS器件（200,300）。 形成在半导体衬底（202,302）上的沟道; 形成在所述沟道上的栅介质层（204,304）; 形成在栅极介电层（204,304）上的栅极导体（206,306）; 以及形成在闸门两侧的源极和漏极; 其中所述栅极导体（206,306）具有用于产生要施加到所述沟道的第一应力的形状，以便调整所述沟道中的载流子的迁移率。 在本发明中，可以通过控制蚀刻工艺参数来调整栅极导体的形状，从而可以方便地调节通道中的应力，同时可以与产生应力的其他机构组合使用以获得期望的 通道压力。

公开(公告)号：US20110089998A1

公开(公告)日：2011-04-21

申请号：US12926475

申请日：2010-11-19

申请人： Huaxiang Yin ,  Youngsoo Park ,  Jaechul Park ,  Sunil Kim

发明人： Huaxiang Yin ,  Youngsoo Park ,  Jaechul Park ,  Sunil Kim

IPC分类号： G05F3/02

CPC分类号： H03K19/01714

摘要： An inverter device includes at least a first transistor connected between a power source node and ground. The first transistor includes a first gate and a first terminal that are internally capacitive-coupled to control a boost voltage at a boost node. The first terminal is one of a first source and a first drain of the first transistor.

公开(公告)号：US07470579B2

公开(公告)日：2008-12-30

申请号：US11557360

申请日：2006-11-07

申请人： Hyuk Lim ,  Takashi Noguchi ,  Jong-man Kim ,  Kyung-bae Park ,  Huaxiang Yin

发明人： Hyuk Lim ,  Takashi Noguchi ,  Jong-man Kim ,  Kyung-bae Park ,  Huaxiang Yin

IPC分类号： H01L21/336

CPC分类号： H01L29/78621 ,  H01L29/66757

摘要： A thin film transistor having an offset or a lightly doped drain (LDD) structure by self alignment and a method of fabricating the same comprises a substrate, a silicon layer disposed on the substrate and including a channel region, a source region and a drain region at both sides of the channel region, and offset regions, each offset regions disposed between the channel region and one of the source and drain regions at both sides of the channel region, a gate insulating layer covering the channel region and the offset regions disposed at both sides of the channel region excluding the source and drain regions, and a gate layer formed on the channel region excluding the offset regions. The thin film transistor has the structure in which an offset or LDD is obtained without an additional mask process.

摘要翻译： 具有通过自对准的偏移或轻掺杂漏极（LDD）结构的薄膜晶体管及其制造方法包括：衬底，设置在衬底上的硅层，并且包括沟道区，源极区和漏极区 在通道区域的两侧和偏移区域，每个偏移区域设置在沟道区域和沟道区域两侧的源极和漏极区域之一之间，覆盖沟道区域的栅极绝缘层和设置在沟道区域的偏移区域 除了源极和漏极区域之外的沟道区域的两侧，以及形成在除偏移区域之外的沟道区域上的栅极层。 薄膜晶体管具有在没有附加掩模处理的情况下获得偏移或LDD的结构。

公开(公告)号：US09691878B2

公开(公告)日：2017-06-27

申请号：US14436892

申请日：2012-10-30

申请人： Haizhou Yin ,  Huilong Zhu ,  Changliang Qin ,  Huaxiang Yin

发明人： Haizhou Yin ,  Huilong Zhu ,  Changliang Qin ,  Huaxiang Yin

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L21/762 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/308 ,  H01L29/161

CPC分类号： H01L29/66636 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/161 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7848

摘要： Provided is a method for manufacturing a MOSFET, including: forming a shallow trench isolation (STI) in a semiconductor substrate to define an active region for the MOSFET; performing etching with the STI as a mask, to expose a surface of the semiconductor substrate, and to protrude a portion of the STI with respect to the surface of the semiconductor substrate, resulting in a protruding portion; forming a first spacer on sidewalls of the protruding portion; forming a gate stack on the semiconductor substrate; forming a second spacer surrounding the gate stack; forming openings in the semiconductor substrate with the STI, the gate stack, the first spacer and the second spacer as a mask; epitaxially growing a semiconductor layer with a bottom surface and sidewalls of each of the openings as a growth seed layer; and performing ion implantation into the semiconductor layer to form source and drain regions.

公开(公告)号：US08889519B2

公开(公告)日：2014-11-18

申请号：US13812499

申请日：2012-10-12

申请人： Xiaolong Ma ,  Huaxiang Yin ,  Zuozhen Fu

发明人： Xiaolong Ma ,  Huaxiang Yin ,  Zuozhen Fu

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L29/161 ,  H01L21/02 ,  H01L21/265 ,  H01L29/10 ,  H01L29/165 ,  H01L21/268 ,  H01L29/51

CPC分类号： H01L29/66477 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02675 ,  H01L21/26506 ,  H01L21/268 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/66651 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7848

摘要： The present invention discloses a semiconductor device, comprising: a substrate, a gate stack structure on the substrate, source and drain regions in the substrate on both sides of the gate stack structure, and a channel region between the source and drain regions in the substrate, characterized in that at least one of the source and drain regions comprises a GeSn alloy. In accordance with the semiconductor device and method for manufacturing the same of the present invention, GeSn stressed source and drain regions with high concentration of Sn is formed by implanting precursors and performing a laser rapid annealing, thus the device carrier mobility of the channel region is effectively enhanced and the device drive capability is further improved.

摘要翻译： 本发明公开了一种半导体器件，包括：衬底，衬底上的栅极堆叠结构，栅极堆叠结构两侧的衬底中的源极和漏极区域以及衬底中的源极和漏极区域之间的沟道区域 其特征在于源区和漏区中的至少一个包括GeSn合金。 根据本发明的半导体器件及其制造方法，通过注入前体并进行激光快速退火形成GeSn应力的高浓度Sn的源区和漏极区，因此沟道区的器件载流子迁移率为 有效提高了设备​​驱动能力。

公开(公告)号：US08853024B2

公开(公告)日：2014-10-07

申请号：US13812498

申请日：2012-08-27

申请人： Huaxiang Yin ,  Jiang Yan ,  Dapeng Chen

发明人： Huaxiang Yin ,  Jiang Yan ,  Dapeng Chen

IPC分类号： H01L21/8238

CPC分类号： H01L27/088 ,  H01L21/82345 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66666 ,  H01L29/7848

摘要： The present invention discloses a method for manufacturing a semiconductor device comprising the steps of: forming a plurality of source and drain regions in a substrate; forming a plurality of gate spacer structures and an interlayer dielectric layer around the gate spacer structures on the substrate, wherein the gate spacer structures enclose a plurality of first gate trenches and a plurality of second gate trenches; sequentially depositing a first gate insulating layer and a second gate insulating layer, a first blocking layer and a second work function regulating layer in the first and second gate trenches; performing selective etching to remove the second work function regulating layer from the first gate trenches to expose the first blocking layer; depositing a first work function regulating layer on the first blocking layer in the first gate trenches and on the second work function regulating layer in the second gate trenches; and depositing a resistance regulating layer on the first work function regulating layer in the first gate trenches and on the first work function regulating layer in the second gate trench.

摘要翻译： 本发明公开了一种制造半导体器件的方法，包括以下步骤：在衬底中形成多个源极和漏极区; 在所述衬底上的所述栅极隔离物结构周围形成多个栅极间隔物结构和层间电介质层，其中所述栅极间隔物结构包围多个第一栅极沟槽和多个第二栅极沟槽; 在第一和第二栅极沟槽中依次沉积第一栅极绝缘层和第二栅极绝缘层，第一阻挡层和第二功函数调节层; 执行选择性蚀刻以从第一栅极沟槽去除第二功函数调节层以暴露第一阻挡层; 在第一栅极沟槽中的第一阻挡层上和第二栅极沟槽中的第二功函数调节层上沉积第一功函数调节层; 以及在第一栅极沟槽中的第一功函数调节层和第二栅沟中的第一功函数调节层上沉积电阻调节层。

公开(公告)号：US08841190B2

公开(公告)日：2014-09-23

申请号：US13519884

申请日：2012-04-10

申请人： Changliang Qin ,  Huaxiang Yin

发明人： Changliang Qin ,  Huaxiang Yin

IPC分类号： H01L29/872

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/045 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

摘要： This invention relates to a MOS device for making the source/drain region closer to the channel region and a method of manufacturing the same, comprising: providing an initial structure, which includes a substrate, an active region, and a gate stack; performing ion implantation in the active region on both sides of the gate stack, such that part of the substrate material undergoes pre-amorphization to form an amorphous material layer; forming a first spacer; with the first spacer as a mask, performing dry etching, thereby forming a recess, with the amorphous material layer below the first spacer kept; performing wet etching using an etchant solution that is isotropic to the amorphous material layer and whose etch rate to the amorphous material layer is greater than or substantially equal to the etch rate to the {100} and {110} surfaces of the substrate material but is far greater than the etch rate to the {111} surface of the substrate material, thus removing the amorphous material layer below the first spacer, such that the substrate material below the amorphous material layer is exposed to the solution and is etched thereby, and in the end, forming a Sigma shaped recess that extends to the nearby region below the gate stack; and epitaxially forming SiGe in the Sigma shaped recess.

摘要翻译： 本发明涉及一种用于使源极/漏极区域更靠近沟道区域的MOS器件及其制造方法，包括：提供包括衬底，有源区域和栅极堆叠的初始结构; 在栅极堆叠的两侧上的有源区中进行离子注入，使得衬底材料的一部分经历预非晶化以形成无定形材料层; 形成第一间隔物; 以第一间隔物作为掩模，进行干蚀刻，从而形成凹部，保持第一间隔物下面的非晶材料层; 使用对非晶材料层各向同性的蚀刻剂溶液进行湿蚀刻，并且其对非晶材料层的蚀刻速率大于或基本上等于对基板材料的{100}和{110}表面的蚀刻速率，但是 远远大于衬底材料的{111}表面的蚀刻速率，从而去除第一间隔物下方的无定形材料层，使得无定形材料层下面的衬底材料暴露于溶液并被蚀刻，并且在 结束，形成延伸到栅堆叠下方的附近区域的Sigma形凹部; 并在Sigma形凹部中外延形成SiGe。

公开(公告)号：US08828881B2

公开(公告)日：2014-09-09

申请号：US13381005

申请日：2011-08-10

申请人： Lingkkuan Meng ,  Huaxiang Yin

发明人： Lingkkuan Meng ,  Huaxiang Yin

IPC分类号： H01L21/3065 ,  H01L21/3105 ,  H01L21/768 ,  H01L29/78

CPC分类号： H01L21/31055 ,  H01L21/76801 ,  H01L29/78

摘要： The invention discloses an etch-back method for planarization at the position-near-interface of an interlayer dielectric (ILD), comprising: depositing or growing a thick layer of SiO2 by the chemical vapor deposition or oxidation method on a surface of a wafer; spin-coating a layer of SOG and then performing a heat treatment to obtain a relatively uniform stack structure; perform an etch-back on the SOG using a plasma etching, and stopping when approaching the position-near-interface of SiO2; performing a plasma etch-back on the remaining SOG/SiO2 structure at the position-near-interface until achieving a desired thickness. Since a two-step etching at the position-near-interface is employed, an extremely good smooth surface of the ILD is obtained. That is, a planar and tidy surface of the ILD is obtained not only in the center region, but also even at the edge of the wafer.

摘要翻译： 本发明公开了一种用于在层间电介质（ILD）的位置 - 接近界​​面处的平坦化的回蚀刻方法，包括：通过化学气相沉积或氧化方法在晶片的表面上沉积或生长厚SiO 2层; 旋涂一层SOG，然后进行热处理以获得相对均匀的堆叠结构; 使用等离子体蚀刻对SOG进行回蚀，并且在接近SiO 2的位置 - 接近界​​面时停止; 在靠近界面的位置处对剩余的SOG / SiO 2结构进行等离子体回蚀，直到达到期望的厚度。 由于在位置 - 接近界​​面处进行两步蚀刻，因此获得了非常好的ILD平滑表面。 也就是说，ILD的平面和整洁的表面不仅在中心区域中获得，而且在晶片的边缘处获得。

公开(公告)号：US20140231923A1

公开(公告)日：2014-08-21

申请号：US14346537

申请日：2012-05-16

申请人： Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

发明人： Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L27/092 ,  H01L21/76232 ,  H01L21/823807 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7846 ,  H01L29/7848

摘要： The present invention provides a semiconductor structure, comprising: a substrate; a gate stack located on the substrate and comprising at least a gate dielectric layer and a gate electrode layer; source/drain regions, located in the substrate on both sides of the gate stack; an STI structure, located in the substrate on both sides of the source/drain regions, wherein the cross-section of the STI structure is trapezoidal, Sigma-shaped or inverted trapezoidal depending on the type of the semiconductor structure. Correspondingly, the present invention further to provides a method of manufacturing the semiconductor structure. In the present invention, STI structures having different shapes can be combined with different stress fillers to apply tensile stress or compressive stress laterally to the channel, which will produce a positive impact on the electron mobility of NMOS and the hole mobility of PMOS and increase the channel current of the device, thereby effectively improving the performance of the semiconductor structure.

摘要翻译： 本发明提供一种半导体结构，包括：基板; 位于所述基板上并且至少包括栅极电介质层和栅极电极层的栅极堆叠; 源极/漏极区域，位于栅极堆叠两侧的衬底中; STI结构，位于源极/漏极区两侧的衬底中，其中根据半导体结构的类型，STI结构的横截面为梯形，Σ形或倒梯形。 相应地，本发明还提供一种制造半导体结构的方法。 在本发明中，具有不同形状的STI结构可以与不同的应力填料组合以向沟道侧向施加拉伸应力或压应力，这将对NMOS的电子迁移率和PMOS的空穴迁移率产生积极影响，并增加 通道电流，从而有效地提高了半导体结构的性能。

公开(公告)号：US20140197376A1

公开(公告)日：2014-07-17

申请号：US13812504

申请日：2012-10-12

申请人： Xiaolong Ma ,  Huaxiang Yin ,  Sen Xu ,  Huilong Zhu

发明人： Xiaolong Ma ,  Huaxiang Yin ,  Sen Xu ,  Huilong Zhu

IPC分类号： H01L29/775

CPC分类号： H01L29/775 ,  H01L29/161 ,  H01L29/165 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66431 ,  H01L29/66545 ,  H01L29/7786

摘要： The present invention discloses a semiconductor device, which comprises a substrate, a buffer layer on the substrate, an inversely doped isolation layer on the buffer layer, a barrier layer on the inversely doped isolation layer, a channel layer on the barrier layer, a gate stack structure on the channel layer, and source and drain regions at both sides of the gate stack structure, characterized in that the buffer layer and/or the barrier layer and/or the inversely doped isolation layer are formed of SiGe alloys or SiGeSn alloys, and the channel layer is formed of a GeSn alloy. The semiconductor device according to the present invention uses a quantum well structure of SiGe/GeSn/SiGe to restrict transportation of carriers, and it introduces a stress through lattice mis-match to greatly increase the carrier mobility, thus improving the device driving capability so as to be adapted to high-speed and high-frequency application.

摘要翻译： 本发明公开了一种半导体器件，其包括衬底，衬底上的缓冲层，缓冲层上的反掺杂隔离层，反掺杂隔离层上的阻挡层，阻挡层上的沟道层，栅极 沟道层上的堆叠结构以及栅极堆叠结构两侧的源极和漏极区域，其特征在于缓冲层和/或势垒层和/或反向掺杂隔离层由SiGe合金或SiGeSn合金形成， 并且沟道层由GeSn合金形成。 根据本发明的半导体器件使用SiGe / GeSn / SiGe的量子阱结构来限制载流子的传输，并且通过晶格失配引入应力以大大增加载流子迁移率，从而提高器件驱动能力，从而 适应高速高频应用。