公开(公告)号：US08828881B2

公开(公告)日：2014-09-09

申请号：US13381005

申请日：2011-08-10

Applicant: Lingkkuan Meng ,  Huaxiang Yin

Inventor： Lingkkuan Meng ,  Huaxiang Yin

IPC: H01L21/3065 ,  H01L21/3105 ,  H01L21/768 ,  H01L29/78

CPC classification number: H01L21/31055 ,  H01L21/76801 ,  H01L29/78

Abstract: The invention discloses an etch-back method for planarization at the position-near-interface of an interlayer dielectric (ILD), comprising: depositing or growing a thick layer of SiO2 by the chemical vapor deposition or oxidation method on a surface of a wafer; spin-coating a layer of SOG and then performing a heat treatment to obtain a relatively uniform stack structure; perform an etch-back on the SOG using a plasma etching, and stopping when approaching the position-near-interface of SiO2; performing a plasma etch-back on the remaining SOG/SiO2 structure at the position-near-interface until achieving a desired thickness. Since a two-step etching at the position-near-interface is employed, an extremely good smooth surface of the ILD is obtained. That is, a planar and tidy surface of the ILD is obtained not only in the center region, but also even at the edge of the wafer.

Abstract translation: 本发明公开了一种用于在层间电介质（ILD）的位置 - 接近界​​面处的平坦化的回蚀刻方法，包括：通过化学气相沉积或氧化方法在晶片的表面上沉积或生长厚SiO 2层; 旋涂一层SOG，然后进行热处理以获得相对均匀的堆叠结构; 使用等离子体蚀刻对SOG进行回蚀，并且在接近SiO 2的位置 - 接近界​​面时停止; 在靠近界面的位置处对剩余的SOG / SiO 2结构进行等离子体回蚀，直到达到期望的厚度。 由于在位置 - 接近界​​面处进行两步蚀刻，因此获得了非常好的ILD平滑表面。 也就是说，ILD的平面和整洁的表面不仅在中心区域中获得，而且在晶片的边缘处获得。

公开(公告)号：US09281398B2

公开(公告)日：2016-03-08

申请号：US14355664

申请日：2012-07-03

Applicant: Huaxiang Yin ,  Changliang Qin ,  Xiaolong Ma ,  Qiuxia Xu ,  Dapeng Chen

Inventor： Huaxiang Yin ,  Changliang Qin ,  Xiaolong Ma ,  Qiuxia Xu ,  Dapeng Chen

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7848 ,  H01L29/1037 ,  H01L29/1095 ,  H01L29/66636 ,  H01L29/7834

Abstract: The present invention discloses a semiconductor device, which comprises a substrate, a gate stack structure on the substrate, a channel region in the substrate under the gate stack structure, and source and drain regions at both sides of the channel region, wherein there is a stressed layer under and at both sides of the channel region, in which the source and drain regions are formed. According to the semiconductor device and the method for manufacturing the same of the present invention, a stressed layer is formed at both sides of and under the channel region made of a silicon-based material so as to act on the channel region, thereby effectively increasing the carrier mobility of the channel region and improving the device performance.

Abstract translation: 本发明公开了一种半导体器件，其包括衬底，衬底上的栅极堆叠结构，栅极堆叠结构下的衬底中的沟道区，以及沟道区两侧的源极和漏极区，其中存在 在形成源极和漏极区的沟道区的下侧和两侧具有应力层。 根据本发明的半导体器件及其制造方法，在由硅系材料制成的沟道区域的两侧和下方形成应力层，以作用于沟道区域，从而有效地增加 通道区域的载波移动性和设备性能的提高。

公开(公告)号：US20150102416A1

公开(公告)日：2015-04-16

申请号：US14396845

申请日：2012-05-17

Applicant: Huaxiang Yin ,  Zuozhen Fu ,  Qiuxia Xu ,  Dapeng Chen

Inventor： Huaxiang Yin ,  Zuozhen Fu ,  Qiuxia Xu ,  Dapeng Chen

IPC: H01L21/8234 ,  H01L29/51 ,  H01L27/092

CPC classification number: H01L21/28088 ,  H01L21/28 ,  H01L21/28008 ,  H01L21/28026 ,  H01L21/28044 ,  H01L21/28079 ,  H01L21/82345 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0928 ,  H01L29/517 ,  H01L29/66515 ,  H01L29/66545

Abstract: A method for manufacturing a dual metal CMOS device comprising: forming a first type metal work function modulation layer in the first gate trench and the second gate trench; forming a second type work function metal diffusion source layer in the first gate trench and the second gate trench; forming a heat isolation layer that shields the region of the first type device; and thermally annealing the regions where the first type device and the second type device are located.

Abstract translation: 一种用于制造双金属CMOS器件的方法，包括：在所述第一栅极沟槽和所述第二栅极沟槽中形成第一类型金属功函数调制层; 在所述第一栅极沟槽和所述第二栅极沟槽中形成第二类型功函数金属扩散源层; 形成屏蔽所述第一类型装置的区域的热隔离层; 并对第一类型器件和第二类型器件所在的区域进行热退火。

公开(公告)号：US08994119B2

公开(公告)日：2015-03-31

申请号：US13520618

申请日：2012-04-11

Applicant: Huaxiang Yin ,  Zuozhen Fu ,  Qiuxia Xu ,  Chao Zhao ,  Dapeng Chen

Inventor： Huaxiang Yin ,  Zuozhen Fu ,  Qiuxia Xu ,  Chao Zhao ,  Dapeng Chen

IPC: H01L27/088 ,  H01L21/8236 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L21/823807 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/7845

Abstract: The present invention discloses a semiconductor device, comprising substrates, a plurality of gate stack structures on the substrate, a plurality of gate spacer structures on both sides of each gate stack structure, a plurality of source and drain regions in the substrate on both sides of each gate spacer structure, the plurality of gate spacer structures comprising a plurality of first gate stack structures and a plurality of second gate stack structures, wherein each of the first gate stack structures comprises a first gate insulating layer, a first work function metal layer, a second work function metal diffusion blocking layer, and a gate filling layer; Each of the second gate stack structures comprises a second gate insulating layer, a first work function metal layer, a second work function metal layer, and a gate filling layer, characterized in that the first work function metal layer has a first stress, and the gate filling layer has a second stress. Two metal gate layers of different types and/or intensity of stress are formed, respectively, thus different stresses are applied to the channel regions of different MOSFETs effectively and accurately, the device carrier mobility is enhanced simply and efficiently, and the device performance is also enhanced.

Abstract translation: 本发明公开了一种半导体器件，包括衬底，衬底上的多个栅极堆叠结构，在每个栅极堆叠结构的两侧上的多个栅极间隔结构，在衬底的两侧的多个源极和漏极区域 每个栅极间隔结构，所述多个栅极间隔结构包括多个第一栅极堆叠结构和多个第二栅极堆叠结构，其中所述第一栅极堆叠结构中的每一个包括第一栅极绝缘层，第一功函数金属层， 第二功函数金属扩散阻挡层和栅极填充层; 每个第二栅极堆叠结构包括第二栅极绝缘层，第一功函数金属层，第二功函数金属层和栅极填充层，其特征在于，第一功函数金属层具有第一应力，并且 栅极填充层具有第二应力。 形成不同类型和/或应力强度的两个金属栅极层，从而有效且准确地对不同MOSFET的沟道区域施加不同的应力，简化高效地提高器件载流子迁移率，器件性能也 增强。

公开(公告)号：US08816326B2

公开(公告)日：2014-08-26

申请号：US13497249

申请日：2011-11-25

Applicant: Huaxiang Yin ,  Jun Luo ,  Chao Zhao ,  Honggang Liu ,  Dapeng Chen

Inventor： Huaxiang Yin ,  Jun Luo ,  Chao Zhao ,  Honggang Liu ,  Dapeng Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/778 ,  H01L29/08

CPC classification number: H01L29/66462 ,  H01L29/0895 ,  H01L29/7391 ,  H01L29/7785 ,  Y10S977/938

Abstract: A semiconductor device, which comprises: a semiconductor substrate; a channel region on the semiconductor substrate, said channel region including a quantum well structure; a source region and a drain region on the sides of the channel region; a gate structure on the channel region; wherein the materials for the channel region, the source region and the drain region have different energy bands, and a tunneling barrier structure exists between the source region and the channel region.

Abstract translation: 一种半导体器件，包括：半导体衬底; 半导体衬底上的沟道区，所述沟道区包括量子阱结构; 在沟道区域的侧面上的源极区域和漏极区域; 通道区域上的栅极结构; 其中用于沟道区，源区和漏区的材料具有不同的能带，并且在源极区域和沟道区域之间存在隧道势垒结构。

公开(公告)号：US08802578B2

公开(公告)日：2014-08-12

申请号：US13695191

申请日：2012-07-26

Applicant: Zuozhen Fu ,  Huaxiang Yin ,  Jiang Yan

Inventor： Zuozhen Fu ,  Huaxiang Yin ,  Jiang Yan

IPC: H01L21/203 ,  H01L21/02 ,  C23C14/34 ,  C23C14/54 ,  C23C14/06 ,  C23C14/18

CPC classification number: H01L21/02186 ,  C23C14/0641 ,  C23C14/18 ,  C23C14/34 ,  C23C14/54 ,  H01L21/2855

Abstract: A method for forming titanium nitride by PVD is disclosed, comprising: generating ions of a noble gas by glow discharge under a vacuum condition that a nitrogen gas and the noble gas are supplied; nitriding a surface of a wafer and a surface of a titanium target with the nitrogen gas; bombarding the surface of the titanium target with the ions of the noble gas after they are accelerated in an electric field so that titanium ions and titanium nitride are sputtered; and forming a titanium nitride layer by depositing titanium nitride on the surface of the wafer in a magnetic field, while titanium ions are injected into the surface of the wafer so that stress is introduced into the titanium nitride layer, wherein non-crystallization fraction of the titanium nitride layer and stress in the titanium nitride layer are increased by increasing kinetic energy of titanium ions which are injected into the surface of the wafer. In the method for forming titanium nitride by PVD according to the present disclosure, kinetic energy of titanium ions which are injected into the surface of the wafer is increased by controlling process parameters so that non-crystallization fraction of the titanium nitride layer and stress in the titanium nitride layer are increased.

Abstract translation: 公开了一种通过PVD形成氮化钛的方法，包括：在供给氮气和惰性气体的真空条件下通过辉光放电产生惰性气体的离子; 用氮气氮化晶片的表面和钛靶的表面; 在惰性气体的离子在电场中加速之后，用钛离子轰击钛靶的表面，从而溅射钛离子和氮化钛; 以及通过在磁场表面上沉积氮化钛而形成氮化钛层，同时将钛离子注入到晶片的表面中，使得应力被引入到氮化钛层中，其中非晶化部分 通过提高注入到晶片表面的钛离子的动能来增加氮化钛层和氮化钛层中的应力。 在根据本公开的通过PVD形成氮化钛的方法中，通过控制工艺参数来增加注入晶片表面的钛离子的动能，使得氮化钛层的非结晶部分和应力在 氮化钛层增加。

公开(公告)号：US08796744B1

公开(公告)日：2014-08-05

申请号：US13812504

申请日：2012-10-12

Applicant: Xiaolong Ma ,  Huaxiang Yin ,  Sen Xu ,  Huilong Zhu

Inventor： Xiaolong Ma ,  Huaxiang Yin ,  Sen Xu ,  Huilong Zhu

IPC: H01L27/148 ,  H01L29/768 ,  H01L29/775

CPC classification number: H01L29/775 ,  H01L29/161 ,  H01L29/165 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66431 ,  H01L29/66545 ,  H01L29/7786

Abstract: The present invention discloses a semiconductor device, which comprises a substrate, a buffer layer on the substrate, an inversely doped isolation layer on the buffer layer, a barrier layer on the inversely doped isolation layer, a channel layer on the barrier layer, a gate stack structure on the channel layer, and source and drain regions at both sides of the gate stack structure, characterized in that the buffer layer and/or the barrier layer and/or the inversely doped isolation layer are formed of SiGe alloys or SiGeSn alloys, and the channel layer is formed of a GeSn alloy. The semiconductor device according to the present invention uses a quantum well structure of SiGe/GeSn/SiGe to restrict transportation of carriers, and it introduces a stress through lattice mis-match to greatly increase the carrier mobility, thus improving the device driving capability so as to be adapted to high-speed and high-frequency application.

Abstract translation: 本发明公开了一种半导体器件，其包括衬底，衬底上的缓冲层，缓冲层上的反掺杂隔离层，反掺杂隔离层上的阻挡层，阻挡层上的沟道层，栅极 沟道层上的堆叠结构以及栅极堆叠结构两侧的源极和漏极区域，其特征在于缓冲层和/或势垒层和/或反向掺杂隔离层由SiGe合金或SiGeSn合金形成， 并且沟道层由GeSn合金形成。 根据本发明的半导体器件使用SiGe / GeSn / SiGe的量子阱结构来限制载流子的传输，并且通过晶格失配引入应力以大大增加载流子迁移率，从而提高器件驱动能力，从而 适应高速高频应用。

公开(公告)号：US20140027783A1

公开(公告)日：2014-01-30

申请号：US13812867

申请日：2012-08-27

Applicant: Huaxiang Yin ,  Changliang Qin ,  Qiuxia Xu ,  Dapeng Chen

Inventor： Huaxiang Yin ,  Changliang Qin ,  Qiuxia Xu ,  Dapeng Chen

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823431 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/7853

Abstract: The present invention discloses a semiconductor device, comprising a plurality of fins located on a substrate and extending along a first direction; a plurality of gate stack structures extending along a second direction and across each of the fins; a plurality of stress layers located in the fins on both sides of the gate stack structures and having a plurality of source and drain regions therein; a plurality of channel regions located between the plurality of source and drain regions along a first direction; characterized in that the plurality of gate stack structures enclose the plurality of channel regions. In accordance with the semiconductor device and the method of manufacturing the same of the present invention, an all-around nanowire metal multi-gate is formed in self-alignment by punching through and etching the fins at which the channel regions are located using a combination of the hard mask and the dummy gate, thus the device performance is enhanced.

Abstract translation: 本发明公开了一种半导体器件，包括位于基片上并沿着第一方向延伸的多个翅片; 多个栅极堆叠结构，沿着第二方向延伸并穿过每个所述散热片; 多个应力层，其位于所述栅极叠层结构的两侧的所述鳍片中，并且在其中具有多个源极和漏极区域; 沿着第一方向位于所述多个源区和漏区之间的多个沟道区; 其特征在于，所述多个栅极堆叠结构包围所述多个沟道区域。 根据本发明的半导体器件及其制造方法，通过使用组合来对通道区域所在的鳍进行冲压和蚀刻来形成全自动纳米线金属多栅极的自对准 的硬掩模和伪栅极，从而提高了器件性能。

公开(公告)号：US20130285127A1

公开(公告)日：2013-10-31

申请号：US13641857

申请日：2012-04-26

Applicant: Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

Inventor： Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66477 ,  H01L21/2255 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7848

Abstract: The present application discloses a method for manufacturing a semiconductor structure, comprises the following steps: providing a substrate and forming a gate stack on the substrate; forming an offset spacer surround the gate stack and a dummy spacer surround the offset spacer; forming the S/D region on both sides of the dummy spacer; removing the dummy spacer and portions of the offset spacer on the surface of the substrate; forming a doped spacer on the sidewall of the offset spacer; forming the S/D extension region by allowing the dopants in doped spacer into the substrate; removing the doped spacer. Accordingly, the present application also discloses a semiconductor structure. In the present disclosure the S/D extension region with high doping concentration and shallow junction depth is formed by the formation of a heavily doped doped spacer, which can be removed in the subsequent procedures, in order to efficiently improve the performance of the semiconductor structure.

Abstract translation: 本申请公开了一种用于制造半导体结构的方法，包括以下步骤：提供衬底并在衬底上形成栅叠层; 形成围绕所述栅极堆叠的偏移间隔物和围绕所述偏移间隔物的虚拟间隔物; 在虚拟间隔物的两侧形成S / D区域; 去除衬垫表面上的虚拟间隔物和偏移间隔物的部分; 在所述偏移间隔物的侧壁上形成掺杂的间隔物; 通过使掺杂间隔物中的掺杂剂进入衬底来形成S / D延伸区域; 去除掺杂间隔物。 因此，本申请还公开了一种半导体结构。 在本公开中，通过形成重掺杂的掺杂间隔物形成具有高掺杂浓度和浅结深度的S / D延伸区，其可以在随后的步骤中去除，以便有效地提高半导体结构的性能 。

公开(公告)号：US08466028B2

公开(公告)日：2013-06-18

申请号：US13322473

申请日：2011-07-27

Applicant: Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

Inventor： Huaxiang Yin ,  Qiuxia Xu ,  Dapeng Chen

IPC: H01L21/336

CPC classification number: H01L29/66795

Abstract: A method for manufacturing a multigate device is provided, comprising: providing a semiconductor substrate; etching the semiconductor substrate to form a protruding fin; etching the semiconductor substrate at the bottom of the fin so as to form a gap between the fin and the semiconductor substrate; forming a dielectric layer which covers the semiconductor substrate and the fin and fills the gap; and etching the dielectric layer so as to expose the top and a portion of sidewalls of the fin. The present invention can realize isolation between fins with a simple process, which costs relatively low and is suitable for massive industrial application.

Abstract translation: 提供了一种制造多栅装置的方法，包括：提供半导体衬底; 蚀刻半导体衬底以形成突出的鳍; 在鳍片的底部蚀刻半导体衬底，以在翅片和半导体衬底之间形成间隙; 形成覆盖所述半导体基板和所述翅片并填充所述间隙的电介质层; 并蚀刻该电介质层以暴露该翅片的顶部和一部分侧壁。 本发明可以通过简单的工艺实现翅片之间的隔离，成本相对较低，适合大规模的工业应用。