公开(公告)号：US08835994B2

公开(公告)日：2014-09-16

申请号：US12791372

申请日：2010-06-01

申请人： Joseph Ervin ,  Jeffrey B. Johnson ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang ,  Yanli Zhang

发明人： Joseph Ervin ,  Jeffrey B. Johnson ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang ,  Yanli Zhang

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L29/786 ,  H01L27/12 ,  H01L21/84 ,  H01L29/66 ,  H01L27/108 ,  H01L21/762

CPC分类号： H01L21/76283 ,  H01L21/84 ,  H01L27/1087 ,  H01L27/10873 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/78603 ,  H01L29/78609 ,  H01L29/78696 ,  H01L29/945

摘要： A structural alternative to retro doping to reduce transistor leakage is provided by providing a liner in a trench, undercutting a conduction channel region in an active semiconductor layer, etching a side, corner and/or bottom of the conduction channel where the undercut exposes semiconductor material in the active layer and replacing the removed portion of the conduction channel with insulator. This shaping of the conduction channel increases the distance to adjacent circuit elements which, if charged, could otherwise induce a voltage and cause a change in back-channel threshold in regions of the conduction channel and narrows and reduces cross-sectional area of the channel where the conduction in the channel is not well-controlled; both of which effects significantly reduce leakage of the transistor.

公开(公告)号：US08669337B2

公开(公告)日：2014-03-11

申请号：US12646333

申请日：2009-12-23

申请人： Ning Lu ,  Sigfredo Gonzalez ,  Emie M. Silvestre ,  Geng Wang

发明人： Ning Lu ,  Sigfredo Gonzalez ,  Emie M. Silvestre ,  Geng Wang

IPC分类号： C08F230/02 ,  C08F220/38

CPC分类号： C08F220/38 ,  C08F228/02 ,  C08F230/02

摘要： The present invention is directed to a network composition having the reaction product of: (i) at least one anionic polymerizable ethylenically unsaturated monomer (I) selected from the group consisting of [CH2═C(R3)C(O)OXa(C2H4O)b(C3H6O)c(C4H8O)d]pP(O)(OY)q(OZ)r where R3═H or alkyl of 1 to about 6 carbon atoms; X=alkyl, aryl, or alkaryl diradical connecting group of 0 to about 9 carbon atoms; a is 0 to about 100; b is 0 to about 100; c is 0 to about 100; d is 0 to about 100; q is 0 to about 2; r is 0 to about 2; p is 1 to about 3 subject to the limitation that p+q+r=3; and Y and Z is H, or metal ion; and CH2═C(R3)C(O)OXa′(C2H4O)b′(C3H6O)c′(C4H8O)d′—SO3—Y) where R3═H or alkyl of from 1 to about 6 carbon atoms; X=alkyl, aryl, or alkaryl diradical connecting group of 0 to about 9 carbon atoms; a′ is 0 to about 100; b′ is 0 to about 100; c′ is 0 to about 100; d′ is 0 to about 100; Y is H, or metal ion; and (ii) one or more additional monomers (II) selected from the group consisting of acrylic acid/acrylate, methacrylic acid/methacrylate, acrylamides, vinyl acetate and styrene, which are copolymerizable with (I); and (iii) a cross-linking agent (III), capable of copolymerizing with (I) and (II).

摘要翻译： 本发明涉及一种具有以下反应产物的网络组合物：（i）至少一种选自[CH2 = C（R3）C（O）OXa（C2H4O））的阴离子可聚合烯属不饱和单体（I） b（C 3 H 6 O）c（C 4 H 8 O）d] pP（O）（OY）q（OZ）r其中R 3 = H或1至约6个碳原子的烷基; X = 0至约9个碳原子的烷基，芳基或烷芳基双基连接基团; a为0〜100; b为0至约100; c为0至约100; d为0至约100; q为0〜2; r为0〜2; p为1至约3，但受限于p + q + r = 3; Y和Z是H或金属离子; 和C 2 = C（R 3）C（O）O X a'（C 2 H 4 O）b'（C 3 H 6 O）c'（C 4 H 8 O）d-SO 3 -Y）其中R 3 = H或1至约6个碳原子的烷基; X = 0至约9个碳原子的烷基，芳基或烷芳基双基连接基团; a'为0至约100; b'为0至约100; c'为0至约100; d'为0至约100; Y是H或金属离子; 和（ii）可与（I）共聚的一种或多种选自丙烯酸/丙烯酸酯，甲基丙烯酸/甲基丙烯酸酯，丙烯酰胺，乙酸乙烯酯和苯乙烯的另外的单体（II）; 和（iii）能够与（I）和（II）共聚的交联剂（III）。

公开(公告)号：US20140061793A1

公开(公告)日：2014-03-06

申请号：US13597752

申请日：2012-08-29

申请人： Chengwen Pei ,  Kangguo Cheng ,  Joseph Ervin ,  Juntao Li ,  Ravi M. Todi ,  Geng Wang

发明人： Chengwen Pei ,  Kangguo Cheng ,  Joseph Ervin ,  Juntao Li ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L27/12 ,  H01L29/06 ,  H01L21/336

CPC分类号： H01L27/0886 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/66795

摘要： A dielectric mandrel structure is formed on a single crystalline semiconductor layer. An amorphous semiconductor material layer is deposited on the physically exposed surfaces of the single crystalline semiconductor layer and surfaces of the mandrel structure. Optionally, the amorphous semiconductor material layer can be implanted with at least one different semiconductor material. Solid phase epitaxy is performed on the amorphous semiconductor material layer employing the single crystalline semiconductor layer as a seed layer, thereby forming an epitaxial semiconductor material layer with uniform thickness. Remaining portions of the epitaxial semiconductor material layer are single crystalline semiconductor fins and thickness of these fins are sublithographic. After removal of the dielectric mandrel structure, the single crystalline semiconductor fins can be employed to form a semiconductor device.

摘要翻译： 介电心轴结构形成在单晶半导体层上。 非晶半导体材料层沉积在单晶半导体层的物理暴露表面和心轴结构的表面上。 可选地，非晶半导体材料层可以注入至少一种不同的半导体材料。 在采用单晶半导体层作为种子层的非晶半导体材料层上进行固相外延，从而形成厚度均匀的外延半导体材料层。 外延半导体材料层的剩余部分是单晶半导体鳍片，并且这些鳍片的厚度是亚光刻的。 在去除介电心轴结构之后，可以采用单晶半导体鳍形成半导体器件。

公开(公告)号：US08637365B2

公开(公告)日：2014-01-28

申请号：US13489572

申请日：2012-06-06

申请人： Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

发明人： Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L21/8242

CPC分类号： H01L29/0649 ,  H01L27/10829 ,  H01L27/10861 ,  H01L27/10867 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/945

摘要： A method of forming improved spacer isolation in deep trench including recessing a node dielectric, a first conductive layer, and a second conductive layer each deposited within a deep trench formed in a silicon-on-insulator (SOI) substrate, to a level below a buried oxide layer of the SOI substrate, and creating an opening having a bottom surface in the deep trench. Further including depositing a spacer along a sidewall of the deep trench and the bottom surface of the opening, and removing the spacer from the bottom surface of the opening. Performing at least one of an ion implantation and an ion bombardment in one direction at an angle into an upper portion of the spacer. Removing the upper portion of the spacer from the sidewall of the deep trench. Depositing a third conductive layer within the opening.

公开(公告)号：US08564069B1

公开(公告)日：2013-10-22

申请号：US13590212

申请日：2012-08-21

申请人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

发明人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi ,  Geng Wang

IPC分类号： H01L27/088

CPC分类号： H01L27/088 ,  H01L21/823412 ,  H01L21/823437 ,  H01L27/027 ,  H01L29/0615 ,  H01L29/78

摘要： Embodiments of the invention relate generally to semiconductor devices and, more particularly, to semiconductor devices having field effect transistors (FETs) with a low body resistance and, in some embodiments, a self-balanced body potential where multiple transistors share same body potential. In one embodiment, the invention includes a field effect transistor (FET) comprising a source within a substrate, a drain within the substrate, and an active gate atop the substrate and between the source and the drain, an inactive gate structure atop the substrate and adjacent the source or the drain, a body adjacent the inactive gate, and a discharge path within the substrate for releasing a charge from the FET, the discharge path lying between the active gate of the FET and the body, wherein the discharge path is substantially perpendicular to a width of the active gate.

摘要翻译： 本发明的实施例大体上涉及半导体器件，更具体地，涉及具有低体电阻的场效应晶体管（FET）的半导体器件，在一些实施例中，具有多个晶体管共享相同体电位的自平衡体电位。 在一个实施例中，本发明包括场效应晶体管（FET），其包括在衬底内的源极，衬底内的漏极，以及位于衬底顶部和源极与漏极之间的有源栅极，在衬底顶部的非活性栅极结构， 邻近源极或漏极，与非活性栅极相邻的主体以及衬底内的用于从FET释放电荷的放电路径，放电路径位于FET的有源栅极和主体之间，其中放电路径基本上 垂直于有源栅极的宽度。

公开(公告)号：US20130185673A1

公开(公告)日：2013-07-18

申请号：US13824144

申请日：2011-09-27

申请人： Ming Cai ,  Ran Sun ,  Geng Wang

发明人： Ming Cai ,  Ran Sun ,  Geng Wang

IPC分类号： G06F3/0481

CPC分类号： G06F3/0481 ,  G01C21/36 ,  G06F3/04815

摘要： An electronic device, a displaying method and a file saving method are described. The electronic device is in a first state and has a display area. The displaying method includes obtaining an image; obtaining an information entry; displaying the image in the display area; and displaying a first type information entry from the information entry in a first region of the display area with a first display effect, and displaying a second type information entry from the information entry in a second region of the display area with a second display effect; wherein the first type information entry is different from the second type information entry.

摘要翻译： 描述电子设备，显示方法和文件保存方法。 电子设备处于第一状态并具有显示区域。 显示方法包括获得图像; 获取信息条目; 在显示区域显示图像; 从所述显示区域的第一区域中的所述信息条目中显示第一类型信息条目，并且具有第二显示效果，在所述显示区域的第二区域中从所述信息条目显示第二类型信息条目; 其中所述第一类型信息条目与所述第二类型信息条目不同。

公开(公告)号：US08473621B2

公开(公告)日：2013-06-25

申请号：US12892608

申请日：2010-09-28

申请人： Jincheng Li ,  Dongming Zhu ,  Jianfeng Zhong ,  Geng Wang ,  Xiao Wang ,  Shumin Cheng

发明人： Jincheng Li ,  Dongming Zhu ,  Jianfeng Zhong ,  Geng Wang ,  Xiao Wang ,  Shumin Cheng

IPC分类号： G06F15/16

CPC分类号： H04L65/1033 ,  H04L65/1016 ,  H04L65/1069 ,  H04L65/4084 ,  H04L65/608

摘要： A method, a system, and an apparatus for creating a Content-on-Demand (CoD) service are disclosed herein. The method includes receiving a Session Initiation Protocol (SIP) service request sent by a User Equipment (UE); converting the SIP service request into a Real-Time Streaming Protocol (RTSP) service request, and sending the RTSP service request to a server; receiving an RTSP service response sent by the server; and converting the RTSP service response into a SIP service response, and sending the SIP service response to the UE to create the CoD service between the UE and the server.

摘要翻译： 本文公开了一种用于创建内容点播（CoD）服务的方法，系统和装置。 该方法包括接收由用户设备（UE）发送的会话发起协议（SIP）服务请求; 将SIP服务请求转换为实时流协议（RTSP）服务请求，并将RTSP服务请求发送到服务器; 接收由服务器发送的RTSP服务响应; 并将RTSP服务响应转换成SIP服务响应，并向UE发送SIP服务响应以在UE与服务器之间创建CoD服务。

公开(公告)号：US20130105898A1

公开(公告)日：2013-05-02

申请号：US13285162

申请日：2011-10-31

申请人： Geng Wang ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi

发明人： Geng Wang ,  Kangguo Cheng ,  Joseph Ervin ,  Chengwen Pei ,  Ravi M. Todi

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66477 ,  H01L21/84 ,  H01L27/1203

摘要： After formation of a gate stack, regions in which a source and a drain are to be formed are recessed through the top semiconductor layer and into an upper portion of a buried single crystalline rare earth oxide layer of a semiconductor-on-insulator (SOI) substrate so that a source trench and drain trench are formed. An embedded single crystalline semiconductor portion epitaxially aligned to the buried single crystalline rare earth oxide layer is formed in each of the source trench and the drain trench to form a recessed source and a recessed drain, respectively. Protrusion of the recessed source and recessed drain above the bottom surface of a gate dielectric can be minimized to reduce parasitic capacitive coupling with a gate electrode, while providing low source resistance and drain resistance through the increased thickness of the recessed source and recessed drain relative to the thickness of the top semiconductor layer.

摘要翻译： 在形成栅极叠层之后，要形成源极和漏极的区域通过顶部半导体层凹陷，并进入绝缘体上半导体（SOI）的掩埋的单晶稀土氧化物层的上部， 衬底，从而形成源极沟槽和漏极沟槽。 在源极沟槽和漏极沟槽的每一个中分别形成外延对齐于埋入的单晶稀土氧化物层的嵌入式单晶半导体部分，以分别形成凹陷源和凹陷漏极。 可以将栅极电介质的底表面之上的凹陷源和凹陷漏极的突起最小化，以减少与栅极电极的寄生电容耦合，同时通过凹陷源和凹陷漏极的增加的厚度提供低的源极电阻和漏极电阻，相对于 顶部半导体层的厚度。

公开(公告)号：US08421139B2

公开(公告)日：2013-04-16

申请号：US12755487

申请日：2010-04-07

申请人： Sivananda Kanakasabapathy ,  Hemanth Jagannathan ,  Geng Wang

发明人： Sivananda Kanakasabapathy ,  Hemanth Jagannathan ,  Geng Wang

IPC分类号： H01L21/00

CPC分类号： H01L27/10826 ,  H01L21/26586 ,  H01L21/845 ,  H01L27/10879 ,  H01L27/10891 ,  H01L27/1211

摘要： A transistor includes a first fin structure and at least a second fin structure formed on a substrate. A deep trench area is formed between the first and second fin structures. The deep trench area extends through an insulator layer of the substrate and a semiconductor layer of the substrate. A high-k metal gate is formed within the deep trench area. A polysilicon layer is formed within the deep trench area adjacent to the metal layer. The polysilicon layer and the high-k metal layer are recessed below a top surface of the insulator layer. A poly strap in the deep trench area is formed on top of the high-k metal gate and the polysilicon material. The poly strap is dimensioned to be below a top surface of the first and second fin structures. The first fin structure and the second fin structure are electrically coupled to the poly strap.

摘要翻译： 晶体管包括第一鳍结构和形成在衬底上的至少第二鳍结构。 在第一和第二翅片结构之间形成深沟槽区域。 深沟槽区域延伸穿过衬底的绝缘体层和衬底的半导体层。 在深沟槽区域内形成高k金属栅极。 在与金属层相邻的深沟槽区域内形成多晶硅层。 多晶硅层和高k金属层凹陷在绝缘体层的顶表面下方。 深沟槽区域中的多晶带形成在高k金属栅极和多晶硅材料的顶部上。 该多晶带的尺寸被设计成在第一和第二鳍结构的顶表面下方。 第一翅片结构和第二翅片结构电耦合到多晶带。

公开(公告)号：US20130032859A1

公开(公告)日：2013-02-07

申请号：US13198152

申请日：2011-08-04

申请人： Chengwen Pei ,  Geng Wang ,  Yanli Zhang

发明人： Chengwen Pei ,  Geng Wang ,  Yanli Zhang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/6656 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636

摘要： A pair of horizontal-step-including trenches are formed in a semiconductor layer by forming a pair of first trenches having a first depth around a gate structure on the semiconductor layer, forming a disposable spacer around the gate structure to cover proximal portions of the first trenches, and by forming a pair of second trenches to a second depth greater than the first depth. The disposable spacer is removed, and selective epitaxy is performed to form an integrated epitaxial source and source extension region and an integrated epitaxial drain and drain extension region. A replacement gate structure can be formed after deposition and planarization of a planarization dielectric layer and subsequent removal of the gate structure and laterally expand the gate cavity over expitaxial source and drain extension regions. Alternately, a contact-level dielectric layer can be deposited directly on the integrated epitaxial regions and contact via structures can be formed therein.

摘要翻译： 通过在半导体层上形成围绕栅极结构的第一深度的一对第一沟槽，在半导体层中形成一对水平台阶包含的沟槽，在栅极结构周围形成一次性间隔物，以覆盖第一 并且通过形成大于第一深度的第二深度的一对第二沟槽。 去除一次性间隔物，并进行选择性外延以形成集成的外延源和源极延伸区域以及集成的外延漏极和漏极延伸区域。 可以在平坦化介电层的沉积和平坦化之后形成替代栅极结构，并且随后去除栅极结构并且在外延源极和漏极延伸区域上横向扩展栅极腔。 或者，可以将接触电介质层直接沉积在集成的外延区上，并且可以在其中形成接触通孔结构。