公开(公告)号：US06819605B2

公开(公告)日：2004-11-16

申请号：US10265254

申请日：2002-10-07

申请人： Yoshiharu Kato

发明人： Yoshiharu Kato

IPC分类号： G11C700

CPC分类号： G11C29/783 ,  G11C29/83

摘要： There is provided a semiconductor memory device and a redundancy judging method which can reduce current consumption when a static-type redundancy judging operation is performed. In case absence of substitute to auxiliary memory cells is set, a non-redundancy setting signal Jdg is set in high logic level and the comparing unit 3 is inactivated and has an operation thereof stopped. Logic fixing unit 5 is connected to respective comparison results E0-n. The logic fixing unit 5 is activated in response to the non-redundancy setting signal Jdg of high logic level and fixes the respective comparison results E0-n to a predetermined logic level. The predetermined logic level is a value which indicates the discordance of the comparison results E0-n and hence, logic composing unit 7 judges that address information and redundancy address information discord with each other. Since the comparison operation is stopped at the comparing unit 3 which constitute an initial stage of the redundancy judging operation for every redundancy judging unit 1 so that the operations of the comparing unit 3 and the logic composing unit 7 are stopped whereby undesired current consumption can be reduced.

摘要翻译： 提供了当执行静态冗余判定操作时可以减少电流消耗的半导体存储器件和冗余判定方法。 在没有设置辅助存储单元的替代的情况下，非冗余设置信号Jdg被设置为高逻辑电平，并且比较单元3被停用，并且其操作停止。 逻辑固定单元5连接到各自的比较结果E0-n。 逻辑固定单元5响应于高逻辑电平的非冗余设置信号Jdg被激活，并且将各个比较结果E0-n固定为预定的逻辑电平。 预定逻辑电平是指示比较结果E0-n不一致的值，因此，逻辑组合单元7判断地址信息和冗余地址信息彼此不一致。 由于在构成每个冗余判定单元1的冗余判定操作的初始阶段的比较单元3中停止比较操作，所以比较单元3和逻辑组合单元7的操作被停止，从而不必要的电流消耗可以 减少

公开(公告)号：US06795328B2

公开(公告)日：2004-09-21

申请号：US10355079

申请日：2003-01-31

申请人： Yoshiharu Kato ,  Kazufumi Komura ,  Satoru Kawamoto

发明人： Yoshiharu Kato ,  Kazufumi Komura ,  Satoru Kawamoto

IPC分类号： G11C506

CPC分类号： G11C7/065 ,  G11C7/18 ,  G11C8/08 ,  G11C2207/065 ,  H01L27/10897

摘要： A semiconductor memory device having a driver transistor for the supply of electric power is provided, which can diminish leakage current during inactivation while ensuring sufficient power supply capability for a sense amplifier during activation. Gate width is provided at every two bit line pair pitches perpendicularly to a bit line direction, and a supply voltage VDD and a reference voltage VSS are fed to PMOS transistors SP0, SP0_ to SP3, sP3_ and NMOS transistors SN0, SN0_ to SN3, SN3_. In driver-dedicated PMOS transistors P1, P2, and NMOS transistors N1, N2, gate width is adjusted using the length of two bit line pair pitches as a maximum value, while gate length is adjusted using an adjusting region &Dgr;L, whereby there can be obtained driver-dedicated MOS transistors P1, P2, N1, and N2 in an appropriately adjusted state with respect to such characteristics contrary to each other as ensuring sufficient current supply capability and diminishing a tailing current.

摘要翻译： 提供了具有用于供电的驱动晶体管的半导体存储器件，其可以在激活期间确保足够的读出放大器的电源能力的同时减少失电期间的漏电流。 栅极宽度设置在垂直于位线方向的每两个位线对间距处，并且电源电压VDD和参考电压VSS被馈送到PMOS晶体管SP0，SP0_至SP3，sP3_和NMOS晶体管SN0，SN0_至SN3，SN3_ 。 在驱动器专用PMOS晶体管P1，P2和NMOS晶体管N1，N2中，使用两个位线对间距的长度作为最大值来调整栅极宽度，而使用调整区域DeltaL来调整栅极长度，由此可以 获得的驱动器专用MOS晶体管P1，P2，N1和N2在适当调整的状态下相对于彼此相反，因为确保足够的电流供应能力和减小尾流电流。

公开(公告)号：US06762617B2

公开(公告)日：2004-07-13

申请号：US10321460

申请日：2002-12-18

申请人： Akihiro Iwase ,  Yoshiharu Kato

发明人： Akihiro Iwase ,  Yoshiharu Kato

IPC分类号： H03K19003

CPC分类号： G11C29/40 ,  G01R31/31701 ,  G11C11/40 ,  G11C29/1201 ,  G11C29/46 ,  G11C2029/0407

摘要： A semiconductor device has a normal operation mode and a test mode. A decision circuit determines whether the device has entered the test mode. A control circuit changes information related to the normal operation mode when a test mode has been entered. If the test mode is accidentally entered, then because the information related to normal operation has been changed, a user can readily determine that the device has entered the test mode.

摘要翻译： 半导体器件具有正常工作模式和测试模式。 决定电路确定设备是否进入测试模式。 当输入测试模式时，控制电路改变与正常操作模式有关的信息。 如果意外输入测试模式，则由于与正常操作有关的信息已经改变，用户可以容易地确定设备已进入测试模式。

公开(公告)号：US06525979B2

公开(公告)日：2003-02-25

申请号：US09968803

申请日：2001-10-03

申请人： Yoshiharu Kato

发明人： Yoshiharu Kato

IPC分类号： G11C700

CPC分类号： G11C7/227 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4091 ,  G11C2207/2281

摘要： A semiconductor memory device including a memory cell for holding charge of first cell information or second cell information, a word line connected to the memory cell for supplying the memory cell with word line voltage, a bit line connected to the memory cell for conveying charge corresponding to the first or second cell information, a dummy cell connected to the bit line for supplying the bit line with complementary charge, and a dummy word line connected to the dummy cell for supplying the dummy cell with dummy word line voltage. The first cell information is read based on the charge conveyed to the bit line from the memory cell when the word line is activated, and the second cell information is read based on the complementary charge supplied to the bit line from the dummy cell when the dummy word line is activated.

公开(公告)号：US06385119B2

公开(公告)日：2002-05-07

申请号：US09772076

申请日：2001-01-30

申请人： Isamu Kobayashi ,  Yoshiharu Kato ,  Kenji Nagai

发明人： Isamu Kobayashi ,  Yoshiharu Kato ,  Kenji Nagai

IPC分类号： G06F126

CPC分类号： G05F3/242

摘要： A method for controlling an internal supply voltage generating circuit reduces power consumption in an active mode. The internal supply voltage generating circuit includes a first voltage-drop regulator, which supplies a relatively large driving power to an internal circuit, and a second voltage-drop regulator, which supplies a relatively small driving power to the internal circuit. First, the second voltage-drop regulator is activated and the first voltage-drop regulator is inactivated in one of a stand-by mode and a power-down mode. Then, at least the first voltage-drop regulator is activated in an active mode, and the first voltage-drop regulator is inactivated in an active pause of the active mode. The first voltage-drop regulator is activated when the active pause is cancelled.

摘要翻译： 用于控制内部电源电压发生电路的方法降低了活动模式下的功耗。 内部电源电压产生电路包括向内部电路提供相对大的驱动功率的第一电压降调节器和向内部电路提供相对小的驱动功率的第二电压降调节器。 首先，第二个电压降调节器被激活，第一个电压降调节器在待机模式和掉电模式之一被禁用。 然后，至少第一电压降调节器在激活模式下被激活，并且第一电压降调节器在激活模式的活动暂停期间被非激活。 当主动暂停被取消时，第一个电压降稳压器被激活。

公开(公告)号：US06194933B1

公开(公告)日：2001-02-27

申请号：US09251471

申请日：1999-02-17

申请人： Kouji Ishino ,  Yoshiharu Kato

发明人： Kouji Ishino ,  Yoshiharu Kato

IPC分类号： H03L700

CPC分类号： H03K5/135 ,  H03K19/01855 ,  H03K19/1738

摘要： An input circuit for use in a semiconductor integrated circuit decreases a phase lag between a clock signal and an input signal. The input circuit includes a first amplifier that receives an external clock signal at a first input and a reference voltage signal at a second input, and generates an amplified clock signal, and a second amplifier that receives an external input signal at a first input and the reference voltage at a second input, and generates an amplified input signal. A latch circuit is connected to the first and second amplifiers and receives the amplified clock signal at its clock input and the amplified input signal at its data input. The first and second amplifiers receive a high voltage supply signal from a common a high potential power supply and a low voltage supply signal from a common low potential power supply.

摘要翻译： 用于半导体集成电路的输入电路减小时钟信号和输入信号之间的相位滞后。 输入电路包括：第一放大器，其接收第一输入端的外部时钟信号和第二输入端的基准电压信号，并产生放大的时钟信号;以及第二放大器，其在第一输入端接收外部输入信号， 参考电压，并产生放大的输入信号。 锁存电路连接到第一和第二放大器，并在其时钟输入处接收放大的时钟信号，并在其数据输入端接收放大的输入信号。 第一和第二放大器接收来自公共高电位电源的高电压电源信号和来自公共低电位电源的低电压电源信号。

公开(公告)号：US5926273A

公开(公告)日：1999-07-20

申请号：US864693

申请日：1997-05-28

申请人： Takaumi Kimura ,  Yoshiharu Kato ,  Zenko Yoshida

发明人： Takaumi Kimura ,  Yoshiharu Kato ,  Zenko Yoshida

IPC分类号： G01J3/42 ,  G01J3/44 ,  G01N21/00 ,  G01N21/17 ,  G01N21/63 ,  G01N21/64 ,  G01N25/16 ,  G01N29/00 ,  G01B9/02

CPC分类号： G01N21/17 ,  G01J3/42 ,  G01J3/4406

摘要： Improved method of laser induced photothermal displacement spectroscopy comprises the steps of applying pulsed laser light to the solution in a sample container, whereupon the light energy absorbed by the solution is converted to heat, with the resulting elastic wave displacing the wall of the sample container by vibrations, detecting the displacement by heterodyne interferometry, and measuring the absorption spectrum of the solution.

摘要翻译： 激光诱导光热置换光谱的改进方法包括以下步骤：将脉冲激光施加到样品容器中的溶液中，由此溶液吸收的光能转换成热，所得到的弹性波将样品容器的壁置于样品容器的壁上 振动，通过外差干涉测量检测位移，并测量溶液的吸收光谱。

公开(公告)号：US5499213A

公开(公告)日：1996-03-12

申请号：US83443

申请日：1993-06-29

申请人： Makoto Niimi ,  Shigemasa Ito ,  Toyonobu Yamada ,  Yoshihiro Takemae ,  Yoshiharu Kato

发明人： Makoto Niimi ,  Shigemasa Ito ,  Toyonobu Yamada ,  Yoshihiro Takemae ,  Yoshiharu Kato

IPC分类号： G11C11/406 ,  G11C7/00

CPC分类号： G11C11/406

摘要： A semiconductor memory device has an oscillator unit for generating refresh pulses, a refresh address detection unit for detecting refreshed addresses and outputting a predetermined signal upon the completion of the refreshing of all addresses, and an output control unit for continuing a self-refresh mode to refresh all addresses according to the signal from the refresh address detection unit, before releasing the self-refresh mode in response to an external signal. Therefore, the refresh operation is continued until all cells are refreshed, thereby data stored in the semiconductor memory device is not lost and is correctly refreshed.

摘要翻译： 半导体存储器件具有用于产生刷新脉冲的振荡器单元，刷新地址检测单元，用于检测刷新的地址并在完成所有地址的刷新时输出预定信号;以及输出控制单元，用于继续自刷新模式 在响应于外部信号释放自刷新模式之前，根据刷新地址检测单元的信号刷新所有地址。 因此，继续刷新操作直到所有单元被刷新，从而存储在半导体存储器件中的数据不会丢失并被正确地刷新。

公开(公告)号：US5309040A

公开(公告)日：1994-05-03

申请号：US73308

申请日：1993-06-08

申请人： Tomio Nakano ,  Yoshiharu Kato ,  Hidenori Nomura

发明人： Tomio Nakano ,  Yoshiharu Kato ,  Hidenori Nomura

IPC分类号： H01L27/02 ,  H03K3/01 ,  G05B24/02 ,  G05F3/16

CPC分类号： H01L27/0218

摘要： In a semiconductor integrated circuit for taking in an external power source voltage from outside the semiconductor chip, the external power source voltage is dropped by a voltage dropping unit installed inside the semiconductor chip and the external power source voltage in the semiconductor integrated circuit, as dropped is supplied as an internal power source voltage to the semiconductor chip and used as the internal power source voltage, a plurality of voltage dropping units are installed for each of a plurality of semiconductor circuit block installed inside the semiconductor chip, and the voltage fluctuation of an internal power source is effectively suppressed in the event that a circuit consuming a very high current is operated.

摘要翻译： 在用于从半导体芯片的外部接收外部电源电压的半导体集成电路中，通过安装在半导体芯片内的降压单元和半导体集成电路中的外部电源电压来降低外部电源电压，如掉线 作为内部电源电压提供给半导体芯片并用作内部电源电压，为安装在半导体芯片内部的多个半导体电路块中的每一个安装多个降压单元，并且电压波动 在消耗非常高的电流的电路被操作的情况下，内部电源被有效地抑制。

公开(公告)号：US5222847A

公开(公告)日：1993-06-29

申请号：US751750

申请日：1991-08-29

申请人： Nobuo Hiyama ,  Yoshiharu Kato

发明人： Nobuo Hiyama ,  Yoshiharu Kato

IPC分类号： B23G5/06

CPC分类号： B23G5/06 ,  B23G2200/48 ,  Y10T408/904 ,  Y10T408/9048

摘要： A tap having a main body having a crest, a heel, and an outer circumference is disclosed. The tap main body has a male screw part at the crest side. At this male screw part, a plurality of grooves opening to the crest and the outer circumference of tap main body is formed. A tap main body has a cutting edge at each ridge part defined by a wall of said plurality of grooves and an outer circumference of a male screw part. These cutting edges each have a crest part and a heel part. The crest part of at least one cutting edge has an axial rake angle which differs from an axial rake angle of the crest part of another cutting edge.