公开(公告)号：US07939892B2

公开(公告)日：2011-05-10

申请号：US12899120

申请日：2010-10-06

Applicant: Hieu Van Tran ,  Anh Ly ,  Sang Thanh Nguyen ,  Vishal Sarin ,  Hung Q. Nguyen ,  William John Saiki ,  Loc B. Hoang

Inventor： Hieu Van Tran ,  Anh Ly ,  Sang Thanh Nguyen ,  Vishal Sarin ,  Hung Q. Nguyen ,  William John Saiki ,  Loc B. Hoang

IPC: H01L23/62 ,  H03K5/08

CPC classification number: G11C11/5621 ,  G11C16/04 ,  G11C29/50 ,  G11C29/50004

Abstract: A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system.

Abstract translation: 可以使用测试装置和方法来检测数字多电平存储器单元系统的电压，电流或信号，或者通过将输入的电压，电流或信号施加到存储器单元系统来测试操作或性能。

公开(公告)号：US07865141B2

公开(公告)日：2011-01-04

申请号：US11808151

申请日：2007-06-07

Applicant: Dave Ta-Wu Liao ,  Steven Donald Edelson

Inventor： Dave Ta-Wu Liao ,  Steven Donald Edelson

IPC: H04B7/00

CPC classification number: G06Q20/3278 ,  G06Q20/32 ,  G06Q20/3229 ,  G06Q20/353

Abstract: The invention presents a chipset for a mobile wallet system in a communication terminal having a SIM socket and a RFID antenna. The chipset includes a wallet module and a controller module. The wallet module has a contactless interface port coupled to the RFID antenna and a wallet memory for storing wallet applications. The controller module, connected to the SIM socket of the communication terminal, has a controller memory stored with SIM function software, mobile wallet application software and software to control the wallet module. The controller module is powered through the SIM socket, and the wallet module is powered through the SIM socket and the RFID antenna.

Abstract translation: 本发明提供了一种具有SIM插座和RFID天线的通信终端中的移动钱包系统的芯片组。 芯片组包括钱包模块和控制器模块。 钱包模块具有耦合到RFID天线的非接触式接口端口和用于存储钱包应用的钱包存储器。 连接到通信终端的SIM插座的控制器模块具有存储有SIM功能软件，移动钱包应用软件和软件的控制器存储器，用于控制钱包模块。 控制器模块通过SIM插座供电，钱包模块通过SIM插座和RFID天线供电。

公开(公告)号：US07860470B2

公开(公告)日：2010-12-28

申请号：US11781198

申请日：2007-07-20

Applicant: Zhiwei Xu ,  Heng-Yu Jian ,  Yi-Cheng Wu ,  Charles Chien

Inventor： Zhiwei Xu ,  Heng-Yu Jian ,  Yi-Cheng Wu ,  Charles Chien

IPC: H03J7/32

CPC classification number: H04B1/30 ,  H03F3/245 ,  H03F3/45183 ,  H03F3/45237 ,  H03F2203/45631 ,  H03F2203/45638

Abstract: A local oscillator (LO) buffer circuit comprises first and second LO buffers arranged in a cross coupled configuration. The first LO buffer generates in-phase output signals in response to in-phase input signals, and quadrature output signals from the second LO buffer. The second LO buffer generates the quadrature output signals in response to quadrature input signals and the in-phase output signals. The LO buffers may include inductive loads. The LO buffers may include MOS transistors or bipolar junction transistors.

Abstract translation: 本地振荡器（LO）缓冲电路包括以交叉耦合配置布置的第一和第二LO缓冲器。 第一LO缓冲器响应于同相输入信号和来自第二LO缓冲器的正交输出信号产生同相输出信号。 第二LO缓冲器响应于正交输入信号和同相输出信号产生正交输出信号。 LO缓冲器可以包括感性负载。 LO缓冲器可以包括MOS晶体管或双极结型晶体管。

公开(公告)号：US07855583B2

公开(公告)日：2010-12-21

申请号：US12493240

申请日：2009-06-28

Applicant: Hieu Van Tran ,  Sang Thanh Nguyen ,  Hung Quoc Nguyen

Inventor： Hieu Van Tran ,  Sang Thanh Nguyen ,  Hung Quoc Nguyen

IPC: G01R19/00

CPC classification number: G11C11/5642 ,  G11C7/06 ,  G11C7/062

Abstract: A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.

Abstract translation: 存储器系统包括用于通过与存储在参考单元中的电压进行比较来检测数据存储单元的内容的读出放大器。 读出放大器可以包括比较器，第一和第二负载电路以及低阻抗电路。 比较器的第一输入耦合到低阻抗电路和参考电压节点。 比较器的第二输入耦合到数据电压节点。 第一负载电路加载耦合到参考电压节点的参考电池。 第二负载电路加载耦合到数据电压节点的数据单元。

公开(公告)号：US07852063B2

公开(公告)日：2010-12-14

申请号：US12133297

申请日：2008-06-04

Applicant: Bun Kobayashi ,  Liyang Zhang ,  Mau-Chung Frank Chang ,  Pei-Ming Daniel Chow

Inventor： Bun Kobayashi ,  Liyang Zhang ,  Mau-Chung Frank Chang ,  Pei-Ming Daniel Chow

IPC: G01R5/22

CPC classification number: G01R21/12 ,  H03G3/3042 ,  H03G2201/708

Abstract: An amplifier circuit comprises a detection power input circuit for receiving an RF signal, and a bias circuit that includes an output for generating a bias signal in response to a reference control voltage. The power detector further comprises a detection circuit for generating a power control voltage having a voltage characteristic that offsets temperature characteristics of the received RF signal. The amplifier circuit further comprises a power amplifier coupled to the bias circuit. The power amplifier includes a driver stage providing the RF signal. The detection circuit compensates temperature variation of the inputted detection voltage of the received RF signal.

Abstract translation: 放大器电路包括用于接收RF信号的检测功率输入电路和包括用于响应于参考控制电压产生偏置信号的输出的偏置电路。 功率检测器还包括用于产生具有抵消接收的RF信号的温度特性的电压特性的功率控制电压的检测电路。 放大器电路还包括耦合到偏置电路的功率放大器。 功率放大器包括提供RF信号的驱动级。 检测电路补偿接收到的RF信号的输入检测电压的温度变化。

公开(公告)号：US20100312926A1

公开(公告)日：2010-12-09

申请号：US12477799

申请日：2009-06-03

Applicant: Siamak Arya ,  Fong-Long Lin ,  Thao Thach Tran

Inventor： Siamak Arya ,  Fong-Long Lin ,  Thao Thach Tran

IPC: G06F3/00 ,  H04B7/005

CPC classification number: H04M1/72527 ,  H04M1/2535

Abstract: A USB switching device can selectively connect between a removable card and a mobile wireless communication device and a computer. The removable card has a first port; the mobile wireless communicating device has a second port while the computer has a third port. The switching device comprises a first full duplex switch having an input and a first output and a second output, and a select port for switching the connection of the input to the first output and the connection of the input to the second output. The switching device further comprises a second full duplex switch having an input and a first output and a second output, and a select port for switching the connection of the input to the first output and the connection of the input to the second output. The switching device further comprises a third full duplex switch having an input and a first output and a second output, and a select port for switching the connection of the input to the first output and the connection of the input to the second output. The input of the first switch is connected to the first port. The input of the second switch is connected to the second port. The input of the third switch is connected to the third port. The first output of the first switch is connected to the second output of the second switch. The second output of the first switch is connected to the first output of the third switch. Finally, the first output of the second switch is connected to the second output of the third switch.

Abstract translation: USB切换设备可以选择性地连接可移动卡与移动无线通信设备和计算机之间。 可拆卸卡具有第一端口; 移动无线通信设备具有第二端口，而计算机具有第三端口。 开关装置包括具有输入和第一输出和第二输出的第一全双工开关，以及用于将输入连接到第一输出和将输入连接到第二输出的选择端口。 开关装置还包括具有输入和第一输出和第二输出的第二全双工开关，以及用于将输入连接到第一输出和将输入连接到第二输出的选择端口。 开关装置还包括具有输入和第一输出和第二输出的第三全双工开关，以及用于将输入连接到第一输出和将输入连接到第二输出的选择端口。 第一开关的输入连接到第一端口。 第二开关的输入连接到第二端口。 第三开关的输入连接到第三端口。 第一开关的第一输出连接到第二开关的第二输出端。 第一开关的第二输出端连接到第三开关的第一输出端。 最后，第二开关的第一输出连接到第三开关的第二输出端。

公开(公告)号：US07848140B2

公开(公告)日：2010-12-07

申请号：US12507783

申请日：2009-07-22

Applicant: Hieu Van Tran ,  Hung Quoc Nguyen ,  Anh Ly ,  Sheng-Hsiung Hsueh ,  Sang Thanh Nguyen ,  Loc B. Hoang ,  Steve Choi ,  Thuan T. Vu

Inventor： Hieu Van Tran ,  Hung Quoc Nguyen ,  Anh Ly ,  Sheng-Hsiung Hsueh ,  Sang Thanh Nguyen ,  Loc B. Hoang ,  Steve Choi ,  Thuan T. Vu

IPC: G11C16/04

CPC classification number: G11C8/10 ,  G11C16/0433 ,  G11C16/08 ,  G11C29/832

Abstract: A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.

Abstract translation: 存储器系统包括布置在扇区中的存储器单元。 对应于扇区的解码器禁止具有缺陷顶门的存储单元。 解码器可以包括用于禁用的低电压或高电压锁存器。 包括顶栅处理算法。 存储器系统可以包括动态顶栅耦合。 包括具有顶栅处理的编程算法和波形。

公开(公告)号：US07829404B2

公开(公告)日：2010-11-09

申请号：US11950345

申请日：2007-12-04

Applicant: Pavel Klinger ,  Amitay Levi

Inventor： Pavel Klinger ,  Amitay Levi

IPC: H01L21/8238

CPC classification number: H01L27/11521 ,  G11C16/0433 ,  H01L27/115 ,  H01L29/42328 ,  H01L29/7885

Abstract: A memory device, and method of making and operating the same, including a substrate of semiconductor material of a first conductivity type, first and second spaced apart regions in the substrate of a second conductivity type with a channel region therebetween, an electrically conductive floating gate having a first portion disposed over and insulated from the channel region and a second portion disposed over and insulated from the first region and including a sharpened edge, an electrically conductive P/E gate having a first portion disposed over and insulated from the first region and a second portion extending up and over the floating gate second portion and insulated therefrom by a first layer of insulation material, and an electrically conductive select gate having a first portion disposed laterally adjacent to the floating gate and disposed over and insulated from the channel region.

Abstract translation: 存储器件及其制造和操作方法，包括第一导电类型的半导体材料的衬底，第二导电类型的衬底中的第一和第二间隔开的区域，其间具有沟道区，导电浮置栅极 具有设置在所述沟道区域上方并与所述沟道区域绝缘的第一部分和设置在所述第一区域上并与所述第一区域绝缘的第二部分，并且包括锐化边缘;导电P / E门，其具有设置在所述第一区域上方并与所述第一区域绝缘的第一部分， 第二部分，其在浮动栅极第二部分上方和上方延伸并且通过第一绝缘材料层与其绝缘;以及导电选择栅极，其具有横向邻近所述浮动栅极设置并设置在所述沟道区域上并与所述沟道区域绝缘的第一部分。

公开(公告)号：US20100254207A1

公开(公告)日：2010-10-07

申请号：US12725370

申请日：2010-03-16

Applicant: Xian Liu ,  Michael James Heinz ,  Eugene Jinglun Tam ,  Michael K. Doan ,  Alexander Kotov ,  Tho Ngoc Dang ,  Jack Edward Frayer ,  Jung Hee Yun ,  Thuan T. Vu

Inventor： Xian Liu ,  Michael James Heinz ,  Eugene Jinglun Tam ,  Michael K. Doan ,  Alexander Kotov ,  Tho Ngoc Dang ,  Jack Edward Frayer ,  Jung Hee Yun ,  Thuan T. Vu

IPC: G11C7/00

CPC classification number: G11C7/00 ,  G11C7/14 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/28 ,  G11C2211/5634

Abstract: A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells.

Abstract translation: 非易失性存储器件具有非易失性存储器单元的阵列，第一多个非易失性存储器参考单元，每个参考单元能够被编程到与其它参考单元不同的参考电平; 和第二多个比较器。 每个比较器可从第一组非易失性存储器参考单元中的一个连接到非易失性存储器单元阵列中的第三多个存储器单元中的一个。

公开(公告)号：US07790518B2

公开(公告)日：2010-09-07

申请号：US12027916

申请日：2008-02-07

Applicant: Bomy Chen ,  Ya-Fen Lin ,  Zhitang Song ,  Songlin Feng

Inventor： Bomy Chen ,  Ya-Fen Lin ,  Zhitang Song ,  Songlin Feng

IPC: H01L21/82

CPC classification number: H01L28/20 ,  H01C17/267 ,  H01L22/22

Abstract: A method of trimming down the volume of a semiconductor resistor element using electrical resistance feedback. After forming conductive material disposed between a pair of electrodes, a voltage is applied to the electrodes to produce an electrical current through the conductive material sufficient to heat and melt away a portion of the conductive material. By reducing the volume of the conductive material, its resistance is increased. The application of the voltage is ceased once the desired dimensions (and thus resistivity) of the conductive material is reached. The resulting semiconductor resistor element could have a fixed resistance, or could have a variable resistance (by using phase change memory material).

Abstract translation: 使用电阻反馈来减少半导体电阻元件的体积的方法。 在形成设置在一对电极之间的导电材料之后，向电极施加电压以产生通过导电材料的电流，足以加热和熔化掉导电材料的一部分。 通过减小导电材料的体积，其电阻增加。 一旦达到导电材料的所需尺寸（因此电阻率），电压的施加就会停止。 所得到的半导体电阻元件可以具有固定电阻，或者可以具有可变电阻（通过使用相变存储器材料）。