公开(公告)号：US10073474B2

公开(公告)日：2018-09-11

申请号：US15251289

申请日：2016-08-30

Applicant: STMicroelectronics (Alps) SAS

Inventor： Patrik Arno ,  Alexandre Balmefrezol

IPC: G06F1/20 ,  G05F1/46

CPC classification number: G05F1/46

Abstract: A method of controlling a current flowing through a load including the steps of: applying a first transfer function representative of the load to a first voltage to obtain a second voltage; applying the second voltage to a first terminal of a circuit for generating the current; sampling a third voltage between first and second terminals of the load; comparing the third voltage with the second voltage; and determining the current to be supplied to the load according to the result of the comparison.

公开(公告)号：US10067550B2

公开(公告)日：2018-09-04

申请号：US15253012

申请日：2016-08-31

Applicant: STMicroelectronics (Alps) SAS

Inventor： Fabien Journet

IPC: G06F1/32 ,  G06F9/38 ,  H04B5/00 ,  G06F1/06

Abstract: Dynamic power control embodiments concern a data processing pipeline. First and second pipeline stages respectively receive first and second clock signals. The first and second pipeline stages are configured to perform first and second operations respectively triggered by first timing edges of the first clock signal and second timing edges of the second clock signal. A clock controller is configured to generate the first and second clock signals. The clock controller is capable of operating in a first mode in which, during a first data processing cycle of the data processing pipeline, a first of the first timing edges is in-phase with a first of the second timing edges. The clock controller is also capable of operating in a second mode in which, during a second data processing cycle of the data processing pipeline, a second of the first timing edges is out of phase with a second of the second timing edges.

公开(公告)号：US20180063638A1

公开(公告)日：2018-03-01

申请号：US15473812

申请日：2017-03-30

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics Design and Application S.R.O. ,  STMicroelectronics (Alps) SAS

Inventor： Jean Claude Bini ,  Dragos Davidescu ,  Igor Cesko ,  Jonathan Cottinet

IPC: H04R3/00 ,  H04R3/04

CPC classification number: H04R3/005 ,  G10K11/346 ,  H04R1/406 ,  H04R3/04 ,  H04R19/005 ,  H04R2201/003 ,  H04R2430/23

Abstract: Several first digital streams of first digital samples at a first sampling frequency are processed to issue corresponding stream that are converted into second digital streams sampled at a second sampling frequency lower than said first sampling frequency. At least one delay to be applied to at least one first digital stream to satisfy a condition on the second digital streams is determined and applied to at least one first digital stream before converting. The converting operation performed is decimation filtering of the first digital streams. The application of the at least one delay to at least one first steam involves skipping a number of first digital samples in the at least one first digital stream. The number skipped depends on the value of the at least one delay. Samples that are skipped are not delivered for decimation filtering.

公开(公告)号：US20180035069A1

公开(公告)日：2018-02-01

申请号：US15725476

申请日：2017-10-05

Applicant: STMicroelectronics (Alps) SAS

Inventor： Serge Hembert

IPC: H04N5/44 ,  G09G5/00

CPC classification number: H04N5/44 ,  G09G5/006 ,  G09G2340/02 ,  G09G2370/20 ,  G09G2370/22 ,  H04R2420/05

Abstract: A video and/or audio decoder provided with a first terminal for supplying an analog audio and/or video signal, including: a first circuit capable of supplying a digital signal which is an image of said analog signal; a digital-to-analog converter capable of receiving as an input said digital signal; an amplifier coupling a second output terminal of the digital-to-analog converter to the first terminal; and a second circuit capable of comparing a signal representative of the voltage or current level on the first terminal with a reference signal, and of deducing therefrom whether the first terminal is connected or not to an analog input terminal of a video signal display and/or audio signal playing device.

公开(公告)号：US09754853B2

公开(公告)日：2017-09-05

申请号：US15050216

申请日：2016-02-22

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： David Auchere ,  Laurent Marechal ,  Laurent Schwarz ,  Yvon Imbs

IPC: H01L23/48 ,  H01L23/31 ,  H01L23/64 ,  H01L23/66 ,  H01L23/00 ,  H01Q1/22 ,  H01L21/48 ,  H01L21/52 ,  H01L21/56 ,  H01L23/13 ,  H01L23/498

CPC classification number: H01Q1/38 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/4889 ,  H01L21/52 ,  H01L21/56 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/315 ,  H01L23/481 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/645 ,  H01L23/66 ,  H01L24/81 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01Q1/2283

Abstract: An electronic device includes a support board having a mounting face and an integrated circuit chip mounted on the mounting face. An encapsulation block embeds the integrated circuit chip, the encapsulation block extending above the integrated circuit chip and around the integrated circuit chip on the mounting face of the support board. The encapsulation block includes a front face with a hole passing through the encapsulation block to uncovering at least part of an electrical contact. A layer made of an electrically conducting material fills the hole to make electrical connection to the electrical contact and further extends over the front face of the encapsulation block.

公开(公告)号：US09698565B1

公开(公告)日：2017-07-04

申请号：US15083921

申请日：2016-03-29

Applicant: STMicroelectronics (Alps) SAS

Inventor： Patrik Arno

IPC: H01S3/00 ,  H01S5/042 ,  H01S5/026 ,  H01S5/062 ,  H01S5/068

CPC classification number: H01S5/042 ,  H01S5/0261 ,  H01S5/06223 ,  H01S5/06808 ,  H01S5/06812 ,  H05B33/0815

Abstract: A diode control device include a first terminal for receiving a first power supply voltage and a second terminal for receiving a second power supply voltage. A circuit of the diode control device applies a regulated voltage on the anode of the diode in response to a control voltage. The control voltage is equal to a preset voltage when a reference voltage is less than or equal to zero. Conversely, when the reference voltage is greater than zero, the control voltage is equal to the sum of the present voltage and a difference between cathode voltage of the diode and the reference voltage.

公开(公告)号：US20170062298A1

公开(公告)日：2017-03-02

申请号：US15050216

申请日：2016-02-22

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： David Auchere ,  Laurent Marechal ,  Laurent Schwarz ,  Yvon Imbs

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L21/52 ,  H01L23/13 ,  H01L23/498

CPC classification number: H01Q1/38 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/4889 ,  H01L21/52 ,  H01L21/56 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/315 ,  H01L23/481 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/645 ,  H01L23/66 ,  H01L24/81 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01Q1/2283

Abstract: An electronic device includes a support board having a mounting face and an integrated circuit chip mounted on the mounting face. An encapsulation block embeds the integrated circuit chip, the encapsulation block extending above the integrated circuit chip and around the integrated circuit chip on the mounting face of the support board. The encapsulation block includes a front face with a hole passing through the encapsulation block to uncovering at least part of an electrical contact. A layer made of an electrically conducting material fills the hole to make electrical connection to the electrical contact and further extends over the front face of the encapsulation block.

Abstract translation: 电子设备包括具有安装面的支撑板和安装在安装面上的集成电路芯片。 封装块嵌入集成电路芯片，封装块在集成电路芯片上方延伸，并围绕集成电路芯片在支撑板的安装面上。 封装块包括具有穿过封装块的孔的前表面以露出至少一部分电触点。 由导电材料制成的层填充孔以与电接触电连接并且进一步在封装块的前表面上延伸。

公开(公告)号：US20160344285A1

公开(公告)日：2016-11-24

申请号：US14959048

申请日：2015-12-04

Applicant: STMicroelectronics (Alps) SAS

Inventor： Vratislav Michal ,  Denis Cottin

IPC: H02M3/07

CPC classification number: H02M3/07 ,  H02M1/08 ,  H02M1/38 ,  H02M3/073

Abstract: A charge-pump device receives two complementary driving signals and a DC signal that are applied to a charge-pump stage containing a full-wave rectifier bridge configured to deliver a DC output signal. The bridge includes active switches controllable by control signals present at two control nodes. The charge-pump device further receives complementary auxiliary signals that are respectively synchronous with the complementary driving signals but have faster edges. Two resistive capacitive filters filter the complementary auxiliary signals to generate control signals at the two control nodes for controlling actuation of the active switches in the bridge.

Abstract translation: 电荷泵装置接收两个互补驱动信号和一个DC信号，该DC信号被施加到电荷泵级，该电荷泵级包含配置成输送DC输出信号的全波整流桥。 该桥包括由两个控制节点上存在的控制信号控制的有源开关。 电荷泵装置还接收互补的辅助信号，其互补驱动信号分别同步但具有较快的边沿。 两个电阻性电容滤波器对互补辅助信号进行滤波，以在两个控制节点处产生控制信号，以控制桥中的有源开关的致动。

公开(公告)号：US12212320B2

公开(公告)日：2025-01-28

申请号：US18296325

申请日：2023-04-05

Applicant: STMICROELECTRONICS S.r.l. ,  STMICROELECTRONICS (ALPS) SAS

Inventor： Antonino Conte ,  Marco Ruta ,  Michelangelo Pisasale ,  Thomas Jouanneau

IPC: H03K19/20 ,  H03K19/0185

Abstract: A level-shifter circuit receives one or more input signals in an input level domain and includes provides at an output node an output signal in an output level domain shifted with respect to the input level domain. The circuit includes output circuitry including a first drive node and a second drive node that receive first and second logical signals so that the output signal has a first output level or a second output level in the output level domain as a function of at least one of the first and second logical signals. The circuit includes first and second shift capacitors coupled to the first and second drive nodes as well as capacitor refresh circuitry.

公开(公告)号：US12124815B2

公开(公告)日：2024-10-22

申请号：US17747101

申请日：2022-05-18

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Pierre Gobin ,  Jeremy Ribeiro De Freitas

IPC: G06F7/548 ,  G06F7/523 ,  G06F7/544

CPC classification number: G06F7/544 ,  G06F7/523

Abstract: A digital signal processor includes K first electronic circuits. The first inputs receive K groups of G successive coefficients of a polynomial. The polynomial are of degree N with N+1 coefficients, where K is a sub-multiple of N+1 greater than or equal to two and G is equal to (N+1)/K. The first electronic circuits are configured to simultaneously implement K respective Horner methods and deliver K output results. A second electronic circuit includes a first input configured to successively receive the output results of the first electronic circuits starting with the output result of the first electronic circuit having processed the highest rank coefficient of the coefficients. A second input is configured to receive a variable X and the second electronic circuit is configured to implement a Horner method and deliver a value of the polynomial for the variable X on the output of the second electronic circuit.