公开(公告)号：US07592225B2

公开(公告)日：2009-09-22

申请号：US11623314

申请日：2007-01-15

申请人： James Kai ,  George Matamis ,  Tuan Duc Pham ,  Masaaki Higashitani ,  Takashi Orimoto

发明人： James Kai ,  George Matamis ,  Tuan Duc Pham ,  Masaaki Higashitani ,  Takashi Orimoto

IPC分类号： H01L21/336 ,  H01L21/3205

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers are formed that serve as a mask for etching one or more layers beneath the spacers. An etch stop pad layer having a material composition substantially similar to the spacer material is provided between a dielectric layer and an insulating sacrificial layer such as silicon nitride. When etching the sacrificial layer, the matched pad layer provides an etch stop to avoid damaging and reducing the size of the dielectric layer. The matched material compositions further provide improved adhesion for the spacers, thereby improving the rigidity and integrity of the spacers.

摘要翻译： 提供了高密度半导体器件及其制造方法。 利用间隔制造技术来形成具有减小的特征尺寸的电路元件，其在一些情况下小于正在使用的工艺的最小可光刻可分辨的元件尺寸。 形成隔板，其用作蚀刻间隔物下面的一个或多个层的掩模。 具有与间隔物材料基本相似的材料组成的蚀刻停止垫层设置在电介质层和诸如氮化硅的绝缘牺牲层之间。 当蚀刻牺牲层时，匹配的焊盘层提供蚀刻停止以避免损坏并减小电介质层的尺寸。 匹配的材料组合物还提供了用于间隔物的改进的粘合性，从而提高了间隔物的刚度和完整性。

公开(公告)号：US07586363B2

公开(公告)日：2009-09-08

申请号：US11955237

申请日：2007-12-12

申请人： Feng Pan ,  Jonathan H. Huynh

发明人： Feng Pan ,  Jonathan H. Huynh

IPC分类号： H03K3/01

CPC分类号： H02M3/073 ,  G11C5/145

摘要： A circuit including a charge pump and regulation circuitry is described. The output of the charge pump is connected to provide a first output signal that is connectable to drive a load. A diode is connected to provide a second output signal of lower voltage from the first output signal. The regulation circuitry is connected to the second output level and is connectable to the charge pump to regulate its output. The circuit also includes a current source connectable from the second line to ground, where control circuitry connects the current source to the second line when the first line is connected to the load.

摘要翻译： 描述了包括电荷泵和调节电路的电路。 电荷泵的输出被连接以提供可连接以驱动负载的第一输出信号。 二极管被连接以提供来自第一输出信号的较低电压的第二输出信号。 调节电路连接到第二输出电平并且可连接到电荷泵以调节其输出。 电路还包括可从第二线路连接到地的电流源，其中当第一线路连接到负载时，控制电路将电流源连接到第二线路。

公开(公告)号：US07586362B2

公开(公告)日：2009-09-08

申请号：US11955221

申请日：2007-12-12

申请人： Feng Pan ,  Jonathan H. Huynh ,  Qui Vi Nguyen

发明人： Feng Pan ,  Jonathan H. Huynh ,  Qui Vi Nguyen

IPC分类号： G05F1/01

CPC分类号： H02M3/07

摘要： Techniques of providing a low output voltage, high current capability charge pump are given. The charge pump has multiple capacitors along with switching circuitry. In an initialization phase, the first plate of each of the capacitors is connected to receive a regulator voltage and the second plate of each capacitor is connected to ground. In a transfer phase, the capacitors are connected in series, where, for each capacitor after the first, the second plate is connected to the first plate of the preceding capacitor in the series. The output voltage of the pump is from the first plate of the last capacitor in the series. Regulation circuitry generates the regulator voltage from a reference voltage to have a value responsive to the output voltage level of the pump.

摘要翻译： 给出了提供低输出电压，高电流能力的电荷泵的技术。 电荷泵具有多个电容器以及开关电路。 在初始化阶段，每个电容器的第一板被连接以接收稳压器电压，并且每个电容器的第二板连接到地。 在转移阶段，电容器串联连接，其中，对于每个电容器，在第一个电容器之后，第二个板件被连接到串联的前一个电容器的第一个板上。 泵的输出电压来自串联的最后一个电容器的第一个板。 调节电路从参考电压产生调节器电压，以响应于泵的输出电压电平。

公开(公告)号：US07583531B2

公开(公告)日：2009-09-01

申请号：US11858902

申请日：2007-09-21

申请人： Jian Chen

发明人： Jian Chen

IPC分类号： G11C11/34

CPC分类号： G11C16/3418 ,  G11C16/3427

摘要： Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in neighboring floating gates (or other neighboring charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To compensate for this coupling, the read process for a given memory cell will take into account the programmed state of a neighbor memory cell if the neighbor memory cell was programmed subsequent to the given memory cell. Techniques for determining whether the neighbor memory cell was programmed before or after the given memory cell are disclosed.

摘要翻译： 存在于非易失性存储单元的浮动栅极（或其他电荷存储元件）上的表观电荷的变化可能发生，因为基于存储在相邻浮动栅极（或其他相邻电荷存储元件）中的电荷的电场的耦合 ）。 在不同时间编程的相邻存储器单元组之间最明显地出现该问题。 为了补偿该耦合，如果相邻存储器单元在给定存储器单元之后被编程，则给定存储器单元的读取过程将考虑相邻存储器单元的编程状态。 公开了用于确定相邻存储器单元是否在给定存储器单元之前或之后被编程的技术。

公开(公告)号：US07577037B2

公开(公告)日：2009-08-18

申请号：US11619513

申请日：2007-01-03

申请人： Yan Li ,  Emilio Yero

发明人： Yan Li ,  Emilio Yero

IPC分类号： G11C16/06

CPC分类号： G11C16/26 ,  G06F12/0893 ,  G06F2212/2022 ,  G06F2212/3042 ,  G11C7/22 ,  G11C16/04 ,  G11C2207/2245 ,  Y02D10/13

摘要： Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the inter-phase pipelining of operations with the same memory, allowing, for example, a read operation to be interleaved between the pulse and verify phases of a write operation. In the exemplary embodiment, the two operations share data latches. In specific examples, at the data latches needed for verification in a multi-level write operation free up, they can be used to store data read from another location during a read performed between steps in the multi-level write. In the exemplary embodiment, the multi-level write need only pause, execute the read, and resume the write at the point where it paused.

摘要翻译： 存在用于通过允许具有相同存储器的操作的相间流水线来提高非易失性存储器件中的性能的方法和电路，从而允许在写入操作的脉冲和验证阶段之间交错读取操作。 在示例性实施例中，两个操作共享数据锁存器。 在具体示例中，在多级写入操作中的验证所需的数据锁存器中，它们可用于存储在多级写入中的步骤之间执行的读取期间从另一位置读取的数据。 在示例性实施例中，多级写入仅需要暂停，执行读取，并在暂停点恢复写入。

公开(公告)号：US07577034B2

公开(公告)日：2009-08-18

申请号：US11861909

申请日：2007-09-26

申请人： Dana Lee ,  Jun Wan

发明人： Dana Lee ,  Jun Wan

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G11C29/00

摘要： A corrective action is taken to adjust for nonlinearities in a program voltage which is applied to a selected word line in a memory device. The nonlinearities result in a non-uniform program voltage step size which can cause over programming or slow programming. A digital to analog converter (DAC) which provides the program voltages can have a nonlinear output, such as when certain code words are input to the DAC. The memory device can be tested beforehand to determine where the nonlinearities occur, and configured to take corrective action when the corresponding code words are input. For example, the DAC may have a nonlinear output when a rollover code word is input, e.g., a when a string of least significant bits in successive code words change from 1's to 0's. The corrective action can include repeating a prior program pulse or adjusting a duration of a program pulse.

摘要翻译： 采取校正动作来调整应用于存储器件中的选定字线的编程电压中的非线性。 非线性导致不均匀的程序电压步长，这可能导致过度编程或缓慢编程。 提供程序电压的数模转换器（DAC）可以具有非线性输出，例如当某些代码字被输入到DAC时。 可以预先测试存储器件以确定非线性发生的位置，并且配置为在输入相应的代码字时采取校正动作。 例如，当输入翻转代码字时，DAC可以具有非线性输出，例如，当连续代码字中的最低有效位的串从1变为0时。 校正动作可以包括重复先前的编程脉冲或调整编程脉冲的持续时间。

公开(公告)号：US07570520B2

公开(公告)日：2009-08-04

申请号：US11616665

申请日：2006-12-27

申请人： Teruhiko Kamei ,  Yan Li

发明人： Teruhiko Kamei ,  Yan Li

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3454

摘要： A trial programming process is performed for a first set of one or more non-volatile storage elements to test usage of the non-volatile storage system. Based on this trial programming, a programming signal is calibrated by adjusting its initial magnitude. The calibrated programming signal is then used to program a second set of non-volatile storage elements (which may or may not include the first set).

摘要翻译： 对第一组一个或多个非易失性存储元件执行试用编程过程以测试非易失性存储系统的使用。 基于该试用编程，通过调整编程信号的初始幅度来校准编程信号。 然后，校准的编程信号用于编程第二组非易失性存储元件（其可以包括或可以不包括第一组）。

公开(公告)号：US07570513B2

公开(公告)日：2009-08-04

申请号：US11534307

申请日：2006-09-22

申请人： Yan Li ,  Seungpil Lee ,  Siu Lung Chan

发明人： Yan Li ,  Seungpil Lee ,  Siu Lung Chan

IPC分类号： G11C11/34

CPC分类号： G11C11/5642 ,  G11C16/26 ,  G11C2211/5621

摘要： A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and program/verify operations. A read or program verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, selective memory cells among the group being sensed in parallel have their conduction currents turned off when they are determined to be in a state not relevant to the current sensing cycle. In another aspect, a power-consuming period is minimized by preemptively starting any operations that would prolong the period. In a program/verify operation cells not to be programmed have their bit lines charged up in the program phase. Power is saved when a set of these bit lines avoids re-charging at every passing of a program phase.

摘要翻译： 能够并行读取和写入具有多个读/写电路的大量存储单元的非易失性存储器件具有降低读取和编程/验证操作期间的功耗的特征。 读取或编程验证操作包括相对于一个或多个分界阈值电压的一个或多个感测周期，以确定存储器状态。 在一个方面，当被确定为处于与当前感测周期无关的状态时，被并联感测的组中的选择性存储单元的导通电流关闭。 另一方面，通过预先启动延长周期的任何操作来最小化功耗周期。 在程序/验证操作中，不编程的单元在程序阶段中将其位线充电。 当一组这些位线避免在每个程序阶段的过程中重新充电时，节省电力。

公开(公告)号：US07567466B2

公开(公告)日：2009-07-28

申请号：US12019564

申请日：2008-01-24

申请人： Raul-Adrian Cernea

发明人： Raul-Adrian Cernea

IPC分类号： G11C7/00

CPC分类号： G11C29/846 ,  G11C29/808 ,  Y10T70/7655

摘要： A memory has defective locations in its user portion replaceable by redundant locations in a redundant portion. Data latches in column circuits of user and redundant portions allow data sensed from or to be written to a memory to be exchanged with a data bus. A remote redundancy scheme has the redundant data available from a central buffer accessible by any number of column circuits. Redundant data buffer circuits enable bus exchange with data from the user data latches except for defective locations when data are taken from the central buffer. In this way only addressing for the user portion is used for bus exchange. Also, accessibility to the redundant data will not be restricted by the locations of the column circuits relative to the redundant data latches and the buffered redundant data can be accessed at a finer granularity than that imposed by the column circuits.

摘要翻译： 存储器在其用户部分中的缺陷位置可由冗余部分中的冗余位置替换。 在用户和冗余部分的列电路中的数据锁存允许从或被写入存储器的数据与数据总线交换。 远程冗余方案具有从任何数量的列电路可访问的中央缓冲器可用的冗余数据。 冗余数据缓冲电路可以实现总线与来自用户数据锁存器的数据的交换，除了从中央缓冲区获取数据时，缺陷位置除外。 以这种方式，仅用于用户部分的寻址用于总线交换。 此外，冗余数据的可访问性不会受到列电路相对于冗余数据锁存器的位置的限制，并且缓冲的冗余数据可以以比由列电路施加的细的粒度访问。

公开(公告)号：US07565478B2

公开(公告)日：2009-07-21

申请号：US11949618

申请日：2007-12-03

申请人： Alan David Bennett ,  Sergey Anatolievich Gorobets ,  Andrew Tomlin ,  Charles Schroter

发明人： Alan David Bennett ,  Sergey Anatolievich Gorobets ,  Andrew Tomlin ,  Charles Schroter

IPC分类号： G06F12/02 ,  G06F13/00

CPC分类号： G11C16/349 ,  G06F12/0246 ,  G06F2212/7205

摘要： A re-programmable non-volatile memory system, such as a flash EEPROM system, having its memory cells grouped into blocks of cells that are simultaneously erasable is operated to perform memory system housekeeping operations in the foreground during execution of a host command, wherein the housekeeping operations are unrelated to execution of the host command. Both one or more such housekeeping operations and execution of the host command are performed within a time budget established for executing that particular command. One such command is to write data being received to the memory. One such housekeeping operation is to level out the wear of the individual blocks that accumulates through repetitive erasing and re-programming.

摘要翻译： 操作一个可重新编程的非易失性存储器系统，例如闪存EEPROM系统，其具有分组为可同时擦除的单元块的存储器单元，以在主机命令的执行期间在前台执行存储器系统管理操作，其中， 内务管理操作与主机命令的执行无关。 在为执行该特定命令建立的时间预算内执行一个或多个此类内务处理操作和主机命令的执行。 一个这样的命令是将正在接收的数据写入存储器。 一个这样的内务处理操作是通过重复擦除和重新编程来平衡累积的各个块的磨损。