公开(公告)号：US5155387A

公开(公告)日：1992-10-13

申请号：US727811

申请日：1991-07-08

申请人： Thomas D. Fletcher ,  Edward A. Burton

发明人： Thomas D. Fletcher ,  Edward A. Burton

IPC分类号： G06F7/50 ,  G06F7/503 ,  H03K17/693 ,  H03K19/0944 ,  H03K19/21

CPC分类号： G06F7/503 ,  H03K17/693 ,  H03K19/09448 ,  H03K19/21

摘要： A circuit employable as a differential multiplexer (10, 310, or 610) or as a differential logic gate (110, 210, 250, 410, or 510) of either the OR/NOR or EXCLUSIVE OR/EXCLUSIVE NOR type contains four pass gates that operate on four circuit input signals and are controlled by two additional circuit input signals. Two of the pass gates drive a bipolar transistor serially coupled to a first FET driven from the other two pass gates. Likewise, the second pair of pass gates drive another bipolar transistor serially coupled to another FET driven from the first pair of pass gates. The bipolar transistors supply respective circuit output signals. The two FETs are of a first polarity. The circuit preferably includes a pair of FETs of a second polarity opposite to the first polarity. The second pair of FETs are arranged so as to provide output pull-up/pull-down assistance for the bipolar transistors.

摘要翻译： OR / NOR或EXCLUSIVE OR / EXCLUSIVE NOR类型的可用作差分多路复用器（10,310或610）或差分逻辑门（110,210,250,410或510）的电路包含四通道 其操作在四个电路输入信号上，并由两个额外的电路输入信号控制。 两个通路驱动双极晶体管串联耦合到从另外两个通过栅极驱动的第一FET。 类似地，第二对通孔驱动另一双极晶体管串联耦合到从第一对通孔驱动的另一个FET。 双极晶体管提供相应的电路输出信号。 两个FET是第一极性。 电路优选地包括与第一极性相反的第二极性的一对FET。 第二对FET被布置成为双极晶体管提供输出上拉/下拉辅助。

公开(公告)号：US5003360A

公开(公告)日：1991-03-26

申请号：US379928

申请日：1989-07-14

申请人： Makoto Okada ,  Naoki Yokoyama

发明人： Makoto Okada ,  Naoki Yokoyama

IPC分类号： H01L29/205 ,  G06F7/50 ,  G06F7/501 ,  H01L29/66 ,  H01L29/80 ,  H01L49/00 ,  H03K19/21 ,  H03M1/80

CPC分类号： G06F7/5013 ,  B82Y10/00 ,  H01L29/66977 ,  H03K19/21 ,  H03M1/802

摘要： A semiconductor functional element is composed of at least one bifurcated branch conductive path coplanar with a heterojunction in a semiconductor with a band discontinuity that produces a potential well, and at least two gate electrodes designed for digital operations and a common electrode facing each other. The gate electrodes cross both paths and the two gate electrodes are located outside of one path and the common electrode is located outside the other path so that electron wave conditions at the heterojunction are locally influenced by an electric field which can be changed by selecting a gate electrode to apply a voltage thereby forming a logic or a functional circuit.

公开(公告)号：US4962341A

公开(公告)日：1990-10-09

申请号：US151423

申请日：1988-02-02

申请人： John A. Schoeff

发明人： John A. Schoeff

IPC分类号： G05F1/577 ,  H03K3/037 ,  H03K19/018 ,  H03K19/082 ,  H03K19/0944 ,  H03K19/173 ,  H03K19/21

CPC分类号： G05F1/577 ,  H03K19/01806 ,  H03K19/082 ,  H03K19/0944 ,  H03K19/09441 ,  H03K19/1735 ,  H03K19/21 ,  H03K19/212 ,  H03K3/037

摘要： Digital logic circuitry designed to operate on a low voltage power supply without substantial transistor saturation thereby achieving lower power and higher opeational speeds. A non-saturating inverter with a low voltage swing can be made with one transistor using standard bipolar production processes and without clamp diodes. The novel circuitry uses logic units which can be modularly combined to form various other logical functions such as inverters, gates, flip-flops, etc. The preferred logic units use a transistor with the base connected by a load resistor to a first current network. The logical input is between the load resistor and base. The emitter is connected either directly or via one or more resistors to a second current network. The first and second power networks are constructed and arranged to provide a voltage-varying profile across both networks which are preferably complementary to provide nearly constant differential voltages across the logic units. The differential voltages can be relatively low, such as less than 1 volt, thus providing low power operation. The power networks provide the biasing voltage for the logic units without separate biasing circuitry. The inverters, gates or other logical units are advantageously grouped into current balanced groups which conduct approximatley constant current between the power networks for a variety of logical code combinations. The total current flow is preferably balanced to be approximatley constant. A means for providing a relatively fixed amount of current matched to equal the balanced total current flow for the logic array is also preferably used. Also disclosed are preferred power networks, logic signal interconnect methods, a preferred gate array and methods for operating such circuits in non-saturating manners.

摘要翻译： 数字逻辑电路设计为在低电压电源上工作，而没有实质的晶体管饱和，从而实现更低的功率和更高的运行速度。 具有低电压摆幅的非饱和型逆变器可以通过一个晶体管使用标准的双极制造工艺，而不需要钳位二极管。 新颖的电路使用逻辑单元，其可以被模块化组合以形成诸如逆变器，门，触发器等的各种其他逻辑功能。优选的逻辑单元使用晶体管，其基极通过负载电阻器连接到第一当前网络。 逻辑输入位于负载电阻和基极之间。 发射极直接或通过一个或多个电阻连接到第二个当前网络。 第一和第二电力网络被构造和布置成在两个网络上提供电压变化的分布，这两个网络优选是互补的，以在逻辑单元上提供几乎恒定的差分电压。 差分电压可以相对较低，例如小于1伏，从而提供低功率操作。 电力网络为逻辑单元提供偏置电压，而无需单独的偏置电路。 逆变器，门或其他逻辑单元有利地被组合成电流平衡组，其对于各种逻辑代码组合在电力网络之间传导近似恒定电流。 总电流优选平衡为近似常数。 还优选使用用于提供与逻辑阵列的平衡总电流相匹配的相对固定量的电流的装置。 还公开了优选的电力网络，逻辑信号互连方法，优选的门阵列和用于以非饱和方式操作这些电路的方法。

公开(公告)号：US4502014A

公开(公告)日：1985-02-26

申请号：US444164

申请日：1982-11-24

申请人： Otto H. Bismarck

发明人： Otto H. Bismarck

IPC分类号： H03K19/21 ,  H03K21/02 ,  H03K21/06

CPC分类号： H03K21/026 ,  H03K19/21

摘要： A circuit responsive to pulses on first and second input signal lines for blocking the propagation of these pulses and inhibiting the production of corresponding pulses on output lines when pulses are present at the same time on the input lines and for producing output pulses corresponding to the pulses on the input lines when there is no coincidence or concurrence of pulses on the two input lines.

摘要翻译： 响应于第一和第二输入信号线上的脉冲的电路，用于阻止这些脉冲的传播，并且当脉冲同时存在于输入线上并且产生对应于脉冲的输出脉冲时，抑制输出线上相应脉冲的产生 在两条输入线上不存在脉冲同步或并行时，在输入线上。

公开(公告)号：US4331925A

公开(公告)日：1982-05-25

申请号：US160349

申请日：1980-06-17

申请人： Otto E. Rittenbach

发明人： Otto E. Rittenbach

IPC分类号： H01Q3/38 ,  H03K19/21 ,  H03K21/40 ,  H03K23/54 ,  H03K21/34

CPC分类号： H01Q3/385 ,  H03K19/21 ,  H03K21/40 ,  H03K23/54

摘要： A pulse train generator comprising a shift register with feedback for proing an output pulse for every m clock pulses applied to the shift register stages. The feedback shift register normally has a maximal length 2.sup.n -1, where n is the number of stages. Clock pulses are applied to the shift register until an all-ONE condition is reached; thereupon, (m-1) additional clock pulses are applied and the states of the register stages can then be sensed. False count correction is obtained by the combination of a detector and an analog integrator.

摘要翻译： 一种脉冲串发生器，包括具有反馈的移位寄存器，用于产生施加到移位寄存器级的每m个时钟脉冲的输出脉冲。 反馈移位寄存器通常具有最大长度2n-1，其中n是级数。 时钟脉冲被施加到移位寄存器，直到达到全1条件; 因此，（m-1）附加时钟脉冲被施加，然后可以感测寄存器级的状态。 通过检测器和模拟积分器的组合获得假计数校正。

公开(公告)号：US4160919A

公开(公告)日：1979-07-10

申请号：US877482

申请日：1978-02-13

申请人： Walter R. Curtice

发明人： Walter R. Curtice

IPC分类号： H03K19/10 ,  H03K19/21 ,  H03K19/32 ,  H03K19/08

CPC分类号： H03K19/21 ,  H03K19/10

摘要： Two input signals, each being at either of two different amplitudes, are coupled to respective Schottky-barrier gates of one transferred electron logic device (TELD) of relatively low transit-time frequency and coupled via a delay means to respective Schottky-barrier gates of another TELD of relatively high transit-time frequency. When the two input signals are at different amplitudes, the TELD connected via the delay means becomes biased to domain formation, thereby causing an output signal having a first value to be produced. When both input signals are at one of the amplitudes, the other TELD becomes biased to domain formation, thereby causing an output signal having a second value to be produced. When both input signals are of the other of the amplitudes, neither TELD is biased to domain formation, thereby causing an output signal having a third value to be produced.

摘要翻译： 两个输入信号（每个处于两个不同幅度的两个）被耦合到相对较低传输时间频率的一个传送电子逻辑器件（TELD）的相应肖特基势垒栅极，并通过延迟装置耦合到相应的肖特基势垒栅极 另一个TELD相对较高的通行时频率。 当两个输入信号处于不同的幅度时，通过延迟装置连接的TELD被偏置成域形成，从而产生具有第一值的输出信号。 当两个输入信号处于幅度之一时，另一个TELD变为偏置于域形成，从而产生具有第二值的输出信号。 当两个输入信号是另一个幅度时，TELD都不会被偏置到域形成，从而产生具有第三值的输出信号。

公开(公告)号：US4099071A

公开(公告)日：1978-07-04

申请号：US747123

申请日：1976-12-03

申请人： David D. Thornburg

发明人： David D. Thornburg

IPC分类号： H03K5/15 ,  H03K17/94 ,  H03K19/00 ,  H03K19/21 ,  H03K17/00 ,  G01R21/02 ,  H01C3/08 ,  H03K19/32

CPC分类号： H03K5/1506 ,  H03K17/94 ,  H03K19/00 ,  H03K19/21

摘要： A tapered resistor heating element is provided which sequentially heats and actuates in a controlled fashion heat sensitive media. In one embodiment a tapered resistor heating element sequentially heats in a controlled fashion heat sensitive switches. Heat sensitive resistors and heat sensitive threshold switches may also be employed in this configuration. This system may be utilized as a meter relay or as described in another embodiment as a scanner. Novel exclusive OR gates are also disclosed which are employed in one embodiment of the scanner of the instant invention.BACKGROUND OF THE INVENTIONThis invention relates generally to scanning devices and more specifically to monolithic electronic scanning devices.It is known that a major problem with matrix addressed displays and the like is the requirement for numerous connections in their implementation between the matrix elements and the ancillary addressing and driving devices. For instance, a display panel with 10.sup.6 matrix elements requires about 2.times.10.sup.3 connections in order to be properly implemented. For devices which are raster scanned, the number of external connections can be greatly reduced provided that the scanning electronics are located on the matrix device panel itself. Such devices, however, are not well known in the art since simple, economical and radically new technologies have not been developed which would effectively allow the production of such devices.Now with the advent of tapered resistor technology more specifically defined in U.S. Ser. No. 747,167, entitled Tapered Resistor Device and filed concurrently herewith which is hereby respectfully incorporated by reference, such novel devices are possible with novel applications of such technology. In the instant recited application, a device is described comprising a tapered resistor element which develops a non-uniform temperature profile on electrical energization which is interacted after being energized with selected heat sensitive media to provide a number of very useful effects and devices which may be employed in a great many applications with ease, simplicity and greater economy than heretofore possible including the scanning apparatus of the instant invention.Generally described therein a conventional resistive device is seen to be a resistive film having a uniform thickness which has been formed into a resistor of a specified width and length. This film is then placed on an insulating substrate which is bonded to a heat sink. When an electrical current I is passed through the resistor the production of Joule heat causes a steady state temperature above ambient .DELTA.T which, if thermal fringing effects are neglected, may be theoretically defined by the relationship ##EQU1## IN WHICH D.sub.S AND K.sub.s are respectively the thickness and thermal conductivity of the substrate and .rho..sub.s is the sheet resistivity of the resistive material measured in ohms/square. (Note: .rho..sub.2 =.rho./d where .rho. is the bulk resistivity of the resistive material.) It is readily seen from this illustration that since the width of the resistor is uniform the local power dissipation and hence the temperature rise is also uniform so that no temperature gradient is established and the unique and utilizable effect of the device of the instant invention is not realized.However, as is seen in FIG. 2 of U.S. Ser. No. 747,167, a device may be provided including a resistive film which significantly has a varying width in the horizontal plane while the thickness remains uniform. This film may be placed on an insulating substrate 2 which in turn is bonded to a heat sink 3. Now it is seen that the width of the resistive element 1 is a monotonically increasing function of position along the length of the element or, in simple terms, the resistive element is tapered. In the event the slope of the taper is gradual over distances comparable with the substrate thickness, equation 1 recited above will still be applicable for a first approximation. When a tapered resistor is energized the local power generation will vary along the length of the resistor so that points of prescribed temperature rise can be made to move along the tapered resistor by varying the current flowing through the device.Although the non-uniformity of the width of the resistive film 1 may vary in any suitable fashion, it is assumed for purposes of this discussion that the taper is linear as is seen in FIG. 1 so that the following relationship is theoretically true:w=w.sub.o +bx .phi.

公开(公告)号：US3714460A

公开(公告)日：1973-01-30

申请号：US3714460D

申请日：1971-09-10

申请人： BELL TELEPHONE LABOR INC

发明人： CLEMETSON W ,  KUROKAWA K

IPC分类号： H03K19/12 ,  H03K19/21 ,  H03K19/32

CPC分类号： H03K19/12 ,  H03K19/21

摘要： An exclusive OR circuit comprises a primary winding having two input terminals and being closely coupled to first and second secondary windings. Rectifying diodes are connected to adjacent ends of the first and second secondary windings, which are adjacent the center of the primary winding. This configuration transmits an output pulse through one of the diodes only upon the application of one input pulse to one of the input terminals, and gives high speed voltage cancellation if coincident pulses are applied. In another embodiment, transistors used in place of the diodes give signal gain.

摘要翻译： 异或电路包括具有两个输入端并且紧密耦合到第一和第二次级绕组的初级绕组。 整流二极管连接到与初级绕组的中心相邻的第一和第二次级绕组的相邻端。 该配置仅在将一个输入脉冲施加到输入端之一时才通过其中一个二极管发送输出脉冲，并且如果施加了一致的脉冲则给出高速电压消除。 在另一个实施例中，代替二极管使用的晶体管产生信号增益。

公开(公告)号：US2992339A

公开(公告)日：1961-07-11

申请号：US62465356

申请日：1956-11-27

申请人： BELL TELEPHONE LABOR INC

发明人： MEYERS STANLEY T

IPC分类号： H03K19/12 ,  H03K19/21

CPC分类号： H03K19/12 ,  H03K19/21

公开(公告)号：US20240361985A1

公开(公告)日：2024-10-31

申请号：US18603806

申请日：2024-03-13

申请人： BEIJING HORIZON INFORMATION TECHNOLOGY CO., LTD.

发明人： Jinnan DING ,  Xiangtao WU

IPC分类号： G06F7/53 ,  G06F7/50 ,  H03K19/21

CPC分类号： G06F7/5318 ,  G06F7/50 ,  H03K19/21

摘要： Disclosed are an operation method of multiplier, an electronic device, and a storage medium. The method includes: determining a plurality of input data sets of the multiplier and an encoding manner for the multiplier; determining at least one low-order input data set in the plurality of input data sets; determining a carry compensation term corresponding to the at least one low-order input data set based on the at least one low-order input data set and the encoding manner; determining a target partial product array based on the carry compensation term corresponding to the at least one low-order input data set and the plurality of input data sets; and determining a product operation result for each input data set based on the target partial product array. According to this disclosure, multiplication operations with multiple precision may be implemented by using one multiplier, thereby reducing hardware resource consumption and hardware area.