公开(公告)号：US20080252384A1

公开(公告)日：2008-10-16

申请号：US11734637

申请日：2007-04-12

申请人： Colin Ka Ho Chow ,  David E. O'Brien

发明人： Colin Ka Ho Chow ,  David E. O'Brien

IPC分类号： H03L7/08

CPC分类号： H03L7/10 ,  H03L7/18 ,  H03L2207/06 ,  H03L2207/12

摘要： A low cost, low phase noise microwave synthesizer includes a DDS modulation circuit and a phase-locked loop. The DDS modulation circuit modulates the output of a DDS to a high frequency. The phase-locked loop downconverts the DDS output and locks the downconverted signal to a relatively low frequency, fixed reference.

摘要翻译： 低成本低相位噪声微波合成器包括DDS调制电路和锁相环。 DDS调制电路将DDS的输出调制到高频。 锁相环下变频DDS输出，并将下变频信号锁定到相对较低频率的固定参考。

公开(公告)号：US20080045162A1

公开(公告)日：2008-02-21

申请号：US11780905

申请日：2007-07-20

申请人： Ahmadreza Rofougaran ,  Maryam Rofougaran ,  Meng-An Pan ,  Hung-Ming Chien ,  Shahla Khorram ,  William Colleran ,  Jacob Rael ,  Masood Syed ,  Brima Ibrahim ,  Stephen Wu ,  Shervin Moloudi

发明人： Ahmadreza Rofougaran ,  Maryam Rofougaran ,  Meng-An Pan ,  Hung-Ming Chien ,  Shahla Khorram ,  William Colleran ,  Jacob Rael ,  Masood Syed ,  Brima Ibrahim ,  Stephen Wu ,  Shervin Moloudi

IPC分类号： H04B1/38

CPC分类号： H03D3/244 ,  H03J2200/04 ,  H03L7/0995 ,  H03L7/18 ,  H03L2207/12 ,  H04B1/707 ,  H04B1/713 ,  H04B17/101 ,  H04B17/14 ,  H04B17/19 ,  H04B17/20

摘要： An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

摘要翻译： 在说明书和附图中描述和示出的本发明的示例性实施例是具有接收器，发射器，本地振荡器（LO）发生器，控制器和自检单元的收发器。 所有这些组件都可以封装以集成到单个IC中，其中包括过滤器和电感器等组件。 用于接收机，发射机和LO发生器的自适应编程和校准的控制器。 自检单元产生用于确定接收机，发射机和LO发生器的增益，频率特性，选择性，本底噪声和失真特性。 要强调的是，该摘要被提供以符合要求摘要的规则，这将允许搜索者或其他读者快速确定技术公开的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

公开(公告)号：US07266171B2

公开(公告)日：2007-09-04

申请号：US10641136

申请日：2003-08-15

申请人： Taizo Yamawaki ,  Masaru Kokubo ,  Tomio Furuya ,  Kazuo Watanabe ,  Julian Hildersley

发明人： Taizo Yamawaki ,  Masaru Kokubo ,  Tomio Furuya ,  Kazuo Watanabe ,  Julian Hildersley

IPC分类号： H03D3/24 ,  H03L7/06 ,  H02M1/02

CPC分类号： H03L7/085 ,  H03L7/10 ,  H03L7/183 ,  H03L2207/12 ,  H04B1/403 ,  H04B1/408

摘要： A communication apparatus includes a phase-locked loop circuit which receives a first signal having a frequency and converts it into an output signal having a transmission frequency and includes a current output type phase comparator which converts a phase difference between the first signal and a second signal into a current signal, a low pass filter which filters the current signal of the current output type phase comparator to produce an output signal a voltage controlled oscillator which produces an output signal having a transmission frequency corresponding to the output signal of the low pass filter the output signal of the voltage controlled oscillator constituting the output signal of the phase-locked loop circuit, a frequency converter which frequency-converts the output signal of the voltage controlled oscillator to produce the second signal, and a current source which supplies a current to an input of the low pass filter.

摘要翻译： 通信装置包括锁相环电路，其接收具有频率的第一信号并将其转换为具有发送频率的输出信号，并且包括电流输出型相位比较器，其转换第一信号和第二信号之间的相位差 将低通滤波器滤波电流输出型相位比较器的电流信号以产生输出信号，该压控振荡器产生具有与低通滤波器的输出信号对应的发送频率的输出信号， 构成锁相环电路的输出信号的压控振荡器的输出信号，对压控振荡器的输出信号进行频率转换以产生第二信号的频率转换器，以及向 输入低通滤波器。

公开(公告)号：US07224736B2

公开(公告)日：2007-05-29

申请号：US10656031

申请日：2003-09-05

申请人： Takaaki Ota

发明人： Takaaki Ota

IPC分类号： H04N7/12 ,  H03L7/00

CPC分类号： H04N5/4401 ,  H03L7/16 ,  H03L7/199 ,  H03L2207/12 ,  H04N5/126 ,  H04N21/4305

摘要： An adaptive clocking mechanism is provided for a digital display system. The digital display system includes a clock recovery system, for recovering a system time clock from a video bit-stream generated at an encoder, and a decoding system for decoding and decompressing the video bit-stream at a frame rate. The adaptive clocking mechanism operates to determine, from video format information transmitted from the encoder, the occurrence of a frame rate at which a transmitted signal is encoded that differs from a frame rate expected by the decoder. Upon such a determination, the adaptive clocking mechanism further operates to select a modifier from a group of modifiers based on format information derived from the video bit stream, including the encoded frame rate. The selected modifier is then applied to a synchronization function of the decoder in a manner to bring the decoder operation into synchronization with the non-expected encoder frame rate.

摘要翻译： 为数字显示系统提供了自适应计时机制。 数字显示系统包括用于从编码器处生成的视频比特流恢复系统时钟的时钟恢复系统和用于以帧速解码和解压缩视频比特流的解码系统。 自适应计时机制的作用是确定从编码器发送的视频格式信息中，发送信号被编码的帧速率的出现与解码器预期的帧速率不同。 在这样的确定的情况下，自适应计时机制进一步操作以基于从包括编码帧速率的视频比特流导出的格式信息从一组修改器中选择修改器。 所选择的修改符然后以使解码器操作与非期望的编码器帧速率同步的方式被应用于解码器的同步功能。

公开(公告)号：US20060267698A1

公开(公告)日：2006-11-30

申请号：US11439732

申请日：2006-05-23

申请人： Ozan Erdogan ,  Jacques Rudell ,  Roger Brockenbrough

发明人： Ozan Erdogan ,  Jacques Rudell ,  Roger Brockenbrough

IPC分类号： H03L7/00

CPC分类号： H03C3/0966 ,  H03C3/0991 ,  H03H11/04 ,  H03L2207/12

摘要： Calibrating a filter is disclosed. The filter is reconfigured as an oscillator during calibration. Switches and/or other implementations of reconfiguring a filter are used to reconfigure the negative feedback loop of the filter to a positive feedback loop. The oscillation parameters are then measured to adjust the components of the filter to achieve an oscillation that corresponds to a desired filter characteristic.

摘要翻译： 公开了校准过滤器。 滤波器在校准期间被重新配置为振荡器。 重新配置滤波器的开关和/或其他实施方式用于将滤波器的负反馈环路重新配置为正反馈环路。 然后测量振荡参数以调整滤波器的分量以实现对应于期望的滤波器特性的振荡。

公开(公告)号：US20060197613A1

公开(公告)日：2006-09-07

申请号：US11415808

申请日：2006-05-02

申请人： Ryan Bunch ,  Alexander Hietala ,  Scott Humphreys

发明人： Ryan Bunch ,  Alexander Hietala ,  Scott Humphreys

IPC分类号： H03L7/00

CPC分类号： H03L7/1976 ,  H03C3/0966 ,  H03L7/23 ,  H03L2207/12

摘要： A linearization system is provided for a Fractional-N Offset Phase Locked Loop (FN-OPLL) in a frequency or phase modulation system. In general, the linearization system processes a modulation signal to provide a linearized modulation signal to a fractional-N divider in a reference path of the FN-OPLL such that a frequency or phase modulation component at the output of the FN-OPLL is substantially linear with respect to the modulation signal.

摘要翻译： 在频率或相位调制系统中为分数N偏移锁相环（FN-OPLL）提供线性化系统。 通常，线性化系统处理调制信号以向FN-OPLL的参考路径中的分数N分频器提供线性调制信号，使得FN-OPLL的输出处的频率或相位调制分量基本上是线性的 相对于调制信号。

公开(公告)号：US07091759B2

公开(公告)日：2006-08-15

申请号：US10858444

申请日：2004-06-01

申请人： Tirdad Sowlati ,  Edward Youssoufian

发明人： Tirdad Sowlati ,  Edward Youssoufian

IPC分类号： H03L7/197

CPC分类号： H03L7/0893 ,  H03L7/093 ,  H03L7/18 ,  H03L2207/12

摘要： A phase-locked loop and method of operation are disclosed. One embodiment includes providing a phase-locked loop, comprising a charge pump system comprising a first charge pump and a second charge pump, the charge pump system configured to provide control signals, a dual path filter, the dual path filter consisting of passive components that are configured to provide summation of control signals, wherein the dual path filter includes a first node coupled between a first charge pump and a first capacitor, wherein the dual path filter includes a second node coupled to a second charge pump through a first resistor, wherein the second node is connected to the first capacitor, and a voltage source coupled to the second node through a second resistor.

摘要翻译： 公开了锁相环和操作方法。 一个实施例包括提供锁相环，包括电荷泵系统，其包括第一电荷泵和第二电荷泵，所述电荷泵系统被配置为提供控制信号双路径滤波器，所述双路径滤波器由无源部件组成， 被配置为提供控制信号的求和，其中所述双路径滤波器包括耦合在第一电荷泵和第一电容器之间的第一节点，其中所述双路径滤波器包括通过第一电阻器耦合到第二电荷泵的第二节点，其中 所述第二节点连接到所述第一电容器，以及通过第二电阻器耦合到所述第二节点的电压源。

公开(公告)号：US20060114068A1

公开(公告)日：2006-06-01

申请号：US10518329

申请日：2002-05-24

申请人： Jacob Midtgaard ,  Oluf Bagger

发明人： Jacob Midtgaard ,  Oluf Bagger

IPC分类号： H03L7/00

CPC分类号： H03L7/07 ,  H03F1/0222 ,  H03F1/0233 ,  H03F1/32 ,  H03F3/72 ,  H03L7/08 ,  H03L7/081 ,  H03L7/087 ,  H03L7/095 ,  H03L7/16 ,  H03L2207/12 ,  H04L27/368

摘要： A phase-locked loop circuit has an output amplifier (27) and a main feedback path from the output of the output amplifier (27). A subsidiary feedback path is provided directly from the output of the circuit's VCO (32). At the start of operation, the output amplifier (27) is disabled and the subsidiary feedback path is used until lock is achieved. Then the output amplifier (27) is enabled and the main feedback loop is used. This avoids spurious outputs from the outer amplifier while to loop locks.

公开(公告)号：US20060111068A1

公开(公告)日：2006-05-25

申请号：US10529971

申请日：2003-05-19

申请人： Hermann Mayer ,  Joerg Hilserecher ,  Guenter Vogel

发明人： Hermann Mayer ,  Joerg Hilserecher ,  Guenter Vogel

IPC分类号： H04B7/00

CPC分类号： H03L7/08 ,  H03C3/0908 ,  H03L1/00 ,  H03L7/185 ,  H03L2207/12

摘要： A driver device for a voltage-controlled oscillator, having an unstable voltage source, a voltage regulator, a driver for generating a control voltage for the oscillator, and a feedback loop which controls the driver as a function of the output signal of the oscillator; the voltage regulator supplying the feedback loop with operating voltage while the driver is powered by the unregulated voltage of the voltage source, and the feedback loop compensates for voltage fluctuations of the voltage source with the aid of the driver.

摘要翻译： 一种用于压控振荡器的驱动器装置，具有不稳定的电压源，电压调节器，用于产生用于振荡器的控制电压的驱动器，以及控制驱动器作为振荡器的输出信号的函数的反馈回路; 当驱动器由电压源的未调节电压供电时，电压调节器向反馈回路提供工作电压，并且反馈环路借助于驱动器来补偿电压源的电压波动。

公开(公告)号：US06996377B1

公开(公告)日：2006-02-07

申请号：US09787380

申请日：1999-09-14

申请人： Taizo Yamawaki ,  Takefumi Endo ,  Kazuo Watanabe ,  Kazuaki Hori ,  Julian Hildersley

发明人： Taizo Yamawaki ,  Takefumi Endo ,  Kazuo Watanabe ,  Kazuaki Hori ,  Julian Hildersley

IPC分类号： H04B1/40

CPC分类号： H03L7/10 ,  H03D13/007 ,  H03L7/08 ,  H03L7/085 ,  H03L7/093 ,  H03L7/099 ,  H03L7/16 ,  H03L2207/12 ,  H04B1/406

摘要： In a PLL circuit, the number of LPFs is reduced to one to reduce mounting area and pin number, and to simplify design. In one embodiment, the PLL circuit includes a variable-gain phase comparator, a mixer, an LPF, VCOs, couplers, and a control circuit to controlling the on/off operation of the VCOs. The variable-gain phase comparator is capable of varying a phase difference gain. The on/off of the operation of the VCOs is controlled by the control circuit so that one of the VCOs is turned off. The phase difference conversion gain is varied in accordance with the sensitivity of the VCOs so the number of LPFs required for the PLL circuit can be reduced to only one.