公开(公告)号：US07263103B2

公开(公告)日：2007-08-28

申请号：US10200189

申请日：2002-07-23

Applicant: Michael Kagan ,  Dafna Levenvirth ,  Yossi Leybovitch

Inventor： Michael Kagan ,  Dafna Levenvirth ,  Yossi Leybovitch

IPC: H04L12/28

CPC classification number: H04L49/9047 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9031

Abstract: A method for network communication includes providing a pool of descriptors to be shared among a plurality of transport service instances used in communicating over a network, each of the descriptors in the pool including a scatter list indicating a buffer that is available in a local memory. When a message containing data to be pushed to the local memory is received over the network on one of transport service instances, one of the descriptors is read from the pool. The data contained in the message are written to the buffer indicated by the scatter list included in the one of the descriptors.

Abstract translation: 一种用于网络通信的方法包括提供要在通过网络进行通信中使用的多个传输服务实例之间共享的描述符池，所述池中的每个描述符包括指示在本地存储器中可用的缓冲区的散列表。 当传输服务实例之一通过网络接收到包含要推送到本地存储器的数据的消息时，将从池中读取一个描述符。 消息中包含的数据被写入由包含在描述符中的散列表指示的缓冲器。

公开(公告)号：US07239645B2

公开(公告)日：2007-07-03

申请号：US10659535

申请日：2003-09-09

Applicant: Salil Suri ,  David Geddes ,  Scott Furey ,  Michael Moretti ,  Thomas Wu

Inventor： Salil Suri ,  David Geddes ,  Scott Furey ,  Michael Moretti ,  Thomas Wu

IPC: H04L12/28 ,  H04L12/56

CPC classification number: H04L49/9021 ,  G06F5/10 ,  H04J3/1617 ,  H04J2203/0082 ,  H04J2203/0089 ,  H04L47/50 ,  H04L47/624 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9047

Abstract: A method and apparatus for bridging network protocols is disclosed. In one embodiment, a data frame is received and stored in a dual-port memory queue by hardware logic. An embedded processor is notified of the data frame once a programmable number of bytes of the data frame have been received and stored. Once notified, the embedded processor may then undertake to read the data frame from the memory queue while the hardware logic is still writing to the memory queue. In one embodiment, the processor may then translate the data frame's protocol and begin transmitting it out over a network connection, all while the data frame's payload is still being received.

Abstract translation: 公开了一种桥接网络协议的方法和装置。 在一个实施例中，数据帧被硬件逻辑接收并存储在双端口存储器队列中。 一旦数据帧的可编程数量的字节已经被接收和存储，嵌入式处理器就被通知数据帧。 一旦通知，当硬件逻辑仍在写入存储器队列时，嵌入式处理器然后可以承担从存储器队列读取数据帧。 在一个实施例中，处理器然后可以转换数据帧的协议，并且开始通过网络连接发送它，同时数据帧的有效载荷仍在被接收。

公开(公告)号：US20070115958A1

公开(公告)日：2007-05-24

申请号：US11562923

申请日：2006-11-22

Applicant: Satoshi KAMIYA ,  Hirokazu OZAKI

Inventor： Satoshi KAMIYA ,  Hirokazu OZAKI

IPC: H04L12/50

CPC classification number: H04L47/10 ,  H04L47/50 ,  H04L47/60 ,  H04L47/6225 ,  H04L49/101 ,  H04L49/1546 ,  H04L49/254 ,  H04L49/3045 ,  H04L49/3063 ,  H04L49/3072 ,  H04L49/503 ,  H04L49/90 ,  H04L49/9047

Abstract: A scheduler and method for scheduling packet forwarding operations is provided. Packet forwarding request information associated with a first set of input port/output port combinations is received. Packet forwarding request information associated with a second set of input port/output port combinations different from the first set of input port/output port combinations is received, where the first set of input port/output port combinations and the second set of input port/output port combinations are selected to not conflict with each other. Packet forwarding for both the first set of input port/output port combinations at a first future time slot and the second set of input port/output port combinations at a second future time slot are simultaneously scheduling at a first scheduler and a second scheduler, respectively, based on the received packet forwarding request information. Reservation information for the first set of input port/output port combinations and the second set of input port/output port combinations is transferred to adjacent schedulers based on a module pattern, where the adjacent schedulers are responsible for scheduling additional sets of input port/output port combinations for the first and second future time slots, respectively.

Abstract translation: 提供了一种用于调度分组转发操作的调度器和方法。 接收与第一组输入端口/输出端口组合相关联的分组转发请求信息。 接收与不同于第一组输入端口/输出端口组合的第二组输入端口/输出端口组合相关联的分组转发请求信息，其中第一组输入端口/输出端口组合和第二组输入端口/ 输出端口组合被选择为不相互冲突。 在第一未来时隙的第一组输入端口/输出端口组合和第二未来时隙处的第二组输入端口/输出端口组合的分组转发分别在第一调度器和第二调度器处同时进行调度 ，基于接收的分组转发请求信息。 基于模块模式将第一组输入端口/输出端口组合和第二组输入端口/输出端口组合的预留信息传输到相邻的调度器，其中相邻调度器负责调度附加的输入端口/输出集合 端口组合分别用于第一和第二未来时隙。

公开(公告)号：US07209991B2

公开(公告)日：2007-04-24

申请号：US10934637

申请日：2004-09-03

Applicant: Christopher L. Chappell

Inventor： Christopher L. Chappell

IPC: G06F13/14

CPC classification number: H04L49/9047 ,  H04L49/90

Abstract: Methods and apparatus, including computer program products, implementing techniques for receiving a request for access to a memory space of an Advanced Switching device, the memory space including a first memory segment and a second memory segment, determining access permissions for the requested memory space, and processing the access request when an access is determined to be permitted. The techniques include identifying a source of the request as a node configuration packet processor, and denying the access if the node configuration packet processor is requesting access to the second memory segment which is assigned to a hidden storage device.

Abstract translation: 包括计算机程序产品的方法和装置，用于接收访问高级交换设备的存储器空间的请求的实现技术，所述存储器空间包括第一存储器段和第二存储器段，确定所请求的存储空间的访问权限， 以及当确定允许访问时处理访问请求。 这些技术包括将请求的源识别为节点配置分组处理器，如果节点配置分组处理器请求访问分配给隐藏存储设备的第二存储器段，则拒绝该访问。

公开(公告)号：US07197043B2

公开(公告)日：2007-03-27

申请号：US11278901

申请日：2006-04-06

Applicant: Enrique Musoll ,  Mario Nemirovsky ,  Stephen Melvin

Inventor： Enrique Musoll ,  Mario Nemirovsky ,  Stephen Melvin

IPC: H04J3/26

CPC classification number: H04L49/9073 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9026 ,  H04L49/9047

Abstract: A hardware/software system is provided for allocating memory in the form of a buffer zone surrounding a data packet to be stored in the memory. The hardware/software system comprises, first and second registers for storing separate values representing in one register, an amount of memory preceding the first line of the data packet to be stored and in the other the amount succeeding the last line of the packet to be stored, a hardware mechanism for allocating the memory according to computational results computed using the register values and the size of a data packet to be stored, and software for processing stored data packet and for writing any new growth data into the designated buffer zones surrounding the data packet.

Abstract translation: 提供了一种硬件/软件系统，用于以围绕要存储在存储器中的数据分组的缓冲区的形式分配存储器。 硬件/软件系统包括：第一和第二寄存器，用于存储表示在一个寄存器中的单独的值，在要存储的数据分组的第一行之前的存储器的量，另一个存储在数据包的最后一行的量 存储用于根据使用寄存器值计算的计算结果和要存储的数据分组的大小分配存储器的硬件​​机制，以及用于处理存储的数据分组并用于将任何新的增长数据写入到指定的缓冲区中的软件 数据包。

公开(公告)号：US20070019659A1

公开(公告)日：2007-01-25

申请号：US11512028

申请日：2006-08-28

Applicant: Donald Primrose ,  I. Denton

Inventor： Donald Primrose ,  I. Denton

IPC: H04L12/56

CPC classification number: H04L49/9078 ,  H04L49/30 ,  H04L49/90 ,  H04L49/9047

Abstract: A buffering structure including at least a first FIFO storage structure to stage at least a selected one of undiverted egress packets and undiverted ingress packets is provided. The buffering structure further includes at least first associated packet drop logic to selectively effectuate head or tail flushes of the first FIFO storage structure. In various embodiments, one or more additional FIFO storage structures are also provided to stage one or more diverted and/or insertion of egress/ingress packets. Those use for staging diverted egress/ingress packets are likewise provided with associated packet drop logic to perform tail flushes of these additional FIFO structures. In one application, the buffering structure is employed by a multi-protocol network processor, which in turn is employed by an optical networking module.

Abstract translation: 提供了包括至少第一FIFO存储结构的缓冲结构，用于对未被引导的出口分组和未发送的入口分组中的至少一个进行分级。 缓冲结构还包括至少第一相关联的分组丢弃逻辑以选择性地实现第一FIFO存储结构的头部或尾部刷新。 在各种实施例中，还提供一个或多个附加FIFO存储结构以对一个或多个转发和/或插入出口/入口分组进行分级。 用于分级转移出口/入口分组的那些同样具有相关联的分组丢弃逻辑以执行这些附加FIFO结构的尾部刷新。 在一个应用中，缓冲结构由多协议网络处理器采用，这又由光网络模块采用。

公开(公告)号：US20070005832A1

公开(公告)日：2007-01-04

申请号：US11171959

申请日：2005-06-29

Applicant: Nai-chih Chang ,  Pak-lung Seto ,  Victor Lau

Inventor： Nai-chih Chang ,  Pak-lung Seto ,  Victor Lau

IPC: G06F5/00

CPC classification number: H04L49/9094 ,  G06F3/0601 ,  G06F5/065 ,  G06F13/385 ,  G06F2003/0692 ,  H04L49/90 ,  H04L49/9047

Abstract: Apparatus and systems, as well as methods and articles, may bridge between a link layer and a transport layer in a multi-lane serial-attached small computer system interface (SCSI)-serial SCSI protocol (SAS-SSP) device. A lane number first-in first-out buffer (FIFO) array may operate to order frame processing such that frames associated with an input-output (IO) stream subset of a plurality of SAS-SSP frames received at a plurality of lane receive buffers are processed in an IO stream subset order.

Abstract translation: 设备和系统以及方法和物品可以在多通道串行连接小型计算机系统接口（SCSI） - 串行SCSI协议（SAS-SSP）设备中的链路层和传输层之间桥接。 车道号先入先出缓冲器（FIFO）阵列可以操作以对帧处理进行排序，使得与在多个通道接收缓冲器处接收的多个SAS-SSP帧的输入 - 输出（IO）流子集相关联的帧 以IO流子集顺序进行处理。

公开(公告)号：US20060291464A1

公开(公告)日：2006-12-28

申请号：US11511944

申请日：2006-08-28

Applicant: Donald Primrose ,  I. Denton

Inventor： Donald Primrose ,  I. Denton

IPC: H04L12/56

CPC classification number: H04L49/9078 ,  H04L49/30 ,  H04L49/90 ,  H04L49/9047

Abstract: A buffering structure including at least a first FIFO storage structure to stage at least a selected one of undiverted egress packets and undiverted ingress packets is provided. The buffering structure further includes at least first associated packet drop logic to selectively effectuate head or tail flushes of the first FIFO storage structure. In various embodiments, one or more additional FIFO storage structures are also provided to stage one or more diverted and/or insertion of egress/ingress packets. Those use for staging diverted egress/ingress packets are likewise provided with associated packet drop logic to perform tail flushes of these additional FIFO structures. In one application, the buffering structure is employed by a multi-protocol network processor, which in turn is employed by an optical networking module.

Abstract translation: 提供了包括至少第一FIFO存储结构的缓冲结构，用于对未被引导的出口分组和未发送的入口分组中的至少一个进行分级。 缓冲结构还包括至少第一相关联的分组丢弃逻辑以选择性地实现第一FIFO存储结构的头部或尾部刷新。 在各种实施例中，还提供一个或多个附加FIFO存储结构以对一个或多个转发和/或插入出口/入口分组进行分级。 用于分级转移出口/入口分组的那些同样具有相关联的分组丢弃逻辑以执行这些附加FIFO结构的尾部刷新。 在一个应用中，缓冲结构由多协议网络处理器采用，这又由光网络模块采用。

公开(公告)号：US20060262791A1

公开(公告)日：2006-11-23

申请号：US11495739

申请日：2006-07-31

Applicant: Shiri Kadambi ,  Shekhar Ambe

Inventor： Shiri Kadambi ,  Shekhar Ambe

IPC: H04L12/56

CPC classification number: H04L12/5601 ,  H04L12/18 ,  H04L12/42 ,  H04L12/46 ,  H04L12/4625 ,  H04L12/4641 ,  H04L12/4645 ,  H04L12/467 ,  H04L12/56 ,  H04L12/5602 ,  H04L29/06 ,  H04L45/00 ,  H04L45/24 ,  H04L45/245 ,  H04L45/742 ,  H04L47/10 ,  H04L47/125 ,  H04L47/2408 ,  H04L47/2441 ,  H04L47/2458 ,  H04L47/30 ,  H04L47/50 ,  H04L47/522 ,  H04L47/525 ,  H04L47/6205 ,  H04L47/6215 ,  H04L47/6225 ,  H04L47/623 ,  H04L49/102 ,  H04L49/103 ,  H04L49/107 ,  H04L49/108 ,  H04L49/109 ,  H04L49/201 ,  H04L49/205 ,  H04L49/254 ,  H04L49/3009 ,  H04L49/3036 ,  H04L49/3072 ,  H04L49/3081 ,  H04L49/309 ,  H04L49/351 ,  H04L49/352 ,  H04L49/354 ,  H04L49/602 ,  H04L49/606 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9047 ,  H04L49/9057 ,  H04L49/9073 ,  H04L67/10 ,  H04L69/14 ,  H04L69/16 ,  H04L69/161 ,  H04L69/323 ,  H04L69/329 ,  H04L2012/5651 ,  H04L2012/5665 ,  H04L2012/5667 ,  H04L2012/5679 ,  H04L2012/568 ,  H04L2012/5682 ,  H04L2012/5683 ,  Y02D50/30 ,  Y10S707/99931 ,  Y10S707/99945

Abstract: A network switch for network communications includes a first data port interface. The first data port interface supports a plurality of data ports transmitting and receiving data at a first data rate. A second data port interface is provided; the second data port interface supports a plurality of data ports transmitting and receiving data at a second data rate. A CPU interface is provided, with the CPU interface configured to communicate with a CPU. An internal memory is provided, and communicates with the first data port interface and the at least one second data port interface. A memory management unit is provided, and includes an external memory interface for communicating data from at least one of the first data port interface and the second data port interface and an external memory. A communication channel is provided, with the communication channel communicating data and messaging information between the first data port interface, the second data port interface, the internal memory, and the memory management unit. A plurality of semiconductor-implemented lookup tables are provided, with the lookup tables including an address resolution lookup/layer three lookup, rules tables, and VLAN tables. One of the data port interfaces is configured to update the address resolution table based on newly learned layer to addresses. An update to an address table associated with an initial data port interface of the first and second data port interfaces results in the initial data port interface sending a synchronization signal to the other address resolution tables in the network switch. As a result, all address resolution tables on the network switch are synchronized on a per entry basis.

公开(公告)号：US20060259572A1

公开(公告)日：2006-11-16

申请号：US11323814

申请日：2005-12-29

Applicant: David Brown

Inventor： David Brown

IPC: G06F15/167

CPC classification number: H04L47/30 ,  H04L47/70 ,  H04L49/103 ,  H04L49/201 ,  H04L49/252 ,  H04L49/9047

Abstract: A switch includes a reserved pool of buffers in a shared memory. The reserved pool of buffers is reserved for exclusive use by an egress port. The switch includes pool select logic which selects a free buffer from the reserved pool for storing data received from an ingress port to be forwarded to the egress port. The shared memory also includes a shared pool of buffers. The shared pool of buffers is shared by a plurality of egress ports. The pool select logic selects a free buffer in the shared pool upon detecting no free buffer in the reserved pool. The shared memory may also include a multicast pool of buffers. The multicast pool of buffers is shared by a plurality of egress ports. The pool select logic selects a free buffer in the multicast pool upon detecting an IP Multicast data packet received from an ingress port.