公开(公告)号：US11113337B2

公开(公告)日：2021-09-07

申请号：US15698911

申请日：2017-09-08

Applicant: Indian Institute of Technology Bombay ,  Tata Consultancy Services

Inventor： Soma Bandyopadhyay ,  Krithivasan Ramamritham

IPC: G01R22/10 ,  G06N5/02 ,  G06F16/903 ,  G06N20/00 ,  G06F3/05

Abstract: Embodiments herein provide a method for imputing sensor data, in a sensor data sequence with missing data based on the semantics learning, where semantics is defined by the constraints of the sensor data features. A candidate value for imputation is determined based on sensor data of corresponding instances of time instants of the sensor data sequence using learning based on semantics of features of the sensor data sequence with missing data. The nearest neighbors search has been applied in similar response data sequence using the data values corresponding to the time instant of missing data in sensor data sequence. In case similar response data sequence is not available imputation is performed based on the distribution pattern of missing data.

公开(公告)号：US10786665B2

公开(公告)日：2020-09-29

申请号：US15695984

申请日：2017-09-05

Applicant: Boston Scientific Neuromodulation Corporation

Inventor： Goran N. Marnfeldt ,  Philip L. Weiss ,  Pujitha Weerakoon ,  David M. Wagenbach ,  Emanuel Feldman ,  Kiran K. Gururaj

IPC: A61N1/00 ,  A61N1/02 ,  A61N1/36 ,  A61N1/05 ,  G06F3/05 ,  H03M1/66

Abstract: Digital-to-analog converter (DAC) circuitry for providing currents at electrodes of an Implantable Pulse Generator (IPG) is disclosed. The DAC circuitry includes at least one PDAC for sourcing current to the electrodes, and at least one NDAC for sinking current from the electrodes. The PDACs are powered with power supplies VH (the compliance voltage) and Vssh in a high power domain, and the NDACs are powered with power supplies Vcc and ground in a low power domain. VH may change during IPG operation, and Vssh preferably also changes with a fixed difference with respect to VH. Digital control signals to the PDACs are formed (and possibly converted into) the high power domain, and transistors used to build the PDACs are biased in the high power domain, and thus may also change with VH. This permits transistors in the PDACs and NDACs to be made from normal low-voltage logic transistors.

公开(公告)号：US10320407B1

公开(公告)日：2019-06-11

申请号：US15890086

申请日：2018-02-06

Applicant: Analog Devices Global Unlimited Company

Inventor： Narsimh Dilip Kamath

IPC: H03M1/00 ,  H03M1/06 ,  G06F3/05 ,  H03M1/14

Abstract: A system having two or more sensing nodes coupled to a control node using a serial communication channel having separate transmit and receive circuits, where each sensing node includes an ADC circuit and a microcontroller, operation of the ADC circuit in each sensing node is concurrently synchronized by the control node using the transmit circuit (e.g., with respect to the control node) of the serial communication channel. The control node can synchronize operation of two or more ADC circuits in separate sensing nodes without using shared clocks or other control signals.

公开(公告)号：US10120432B2

公开(公告)日：2018-11-06

申请号：US15096016

申请日：2016-04-11

Applicant: LG DISPLAY CO., LTD.

Inventor： Kyungjin Jang

IPC: G06F3/045 ,  G06F1/32 ,  G06F3/044 ,  G06F3/041 ,  G06F3/05

Abstract: A touch sensing system and a method of controlling power consumption thereof are disclosed. The touch sensing system includes a plurality of sensing units, which sample a voltage received from a touch screen and accumulate the sampled voltage, and a plurality of analog-to-digital converters converting an output of the sensing units into digital data. The sensing units and the analog-to-digital converters are divided into a plurality of groups in an idle state. Each of the plurality of groups includes at least two sensing units and one analog-to-digital converter. At least one sensing unit included in at least one group is powered down in the idle state. An analog-to-digital converter is powered on during the group it belongs to is powered on.

公开(公告)号：US09977489B2

公开(公告)日：2018-05-22

申请号：US15156670

申请日：2016-05-17

Applicant: West Virginia University

Inventor： Brandon Michael Kelly ,  Brandon David Rumberg ,  David W. Graham

IPC: G06F1/04 ,  G06F1/14 ,  G06F1/32 ,  G06F1/08 ,  G06F3/05 ,  G06F1/10 ,  G06F13/24 ,  G06F9/44 ,  H04L12/24 ,  H04W52/02

CPC classification number: G06F1/3293 ,  G06F1/08 ,  G06F1/10 ,  G06F1/3203 ,  G06F1/3275 ,  G06F3/05 ,  G06F9/4418 ,  G06F13/24 ,  H04L41/0816 ,  H04W52/02 ,  Y02D10/14 ,  Y02D70/00

Abstract: Aspects of a low power memory buffer are described. In one embodiment, a sampling rate of a signal is adjusted to identify extrema of a signal. An extrema pulse is generated and, in response to the extrema pulse, a time segment and potential value of the signal are stored in a memory. In other aspects, rising and falling slopes of the signal are tracked to identify a local maximum and a local minimum of the signal. In this scenario, an extrema pulse is generated for each of the local maximum and minimum, and time segment and potential values are stored for the local maximum and minimum. Generally, the storage of analog values of the signal at an adjusted sampling rate is achieved with low power, and the signal may be reconstructed at a later time.

公开(公告)号：US09715480B1

公开(公告)日：2017-07-25

申请号：US13847521

申请日：2013-03-20

Applicant: Charles H. Tally ,  Paul David Swanson ,  Richard L. Waters

Inventor： Charles H. Tally ,  Paul David Swanson ,  Richard L. Waters

IPC: G05B11/42 ,  G06F17/15 ,  G06F17/17 ,  G06F3/05 ,  H03K17/955 ,  G01P15/125 ,  G01P15/135 ,  G01C19/5705

CPC classification number: G06F17/15 ,  G01P15/097 ,  G01P15/125 ,  G01P15/135 ,  H03B5/30 ,  G01C7/04

Abstract: A method for approximating the behavior of a periodic parameter of a time-domain device in response to a perturbation, the method comprising the following steps: collecting data points at discreet times, wherein each data point represents a measurement of the parameter; dividing the time domain into intervals, each given interval containing at least one data point sampled during the given interval; fitting a polynomial function to the data points of each interval such that each interval has a corresponding polynomial function that is time-centered on the interval's center point and that accurately describes the parameter behavior over that interval; and stitching together the polynomial functions piece-wise to create an analytic approximation of the behavior of the system parameter over the entire time domain.

公开(公告)号：US20160357321A1

公开(公告)日：2016-12-08

申请号：US15170136

申请日：2016-06-01

Applicant: Japan Display Inc.

Inventor： Daisuke ITO ,  Toshihiko FUJIWARA ,  Hayato KURASAWA ,  Hiroshi MIZUHASHI

IPC: G06F3/041 ,  G09G3/36 ,  G06F3/05 ,  G02F1/1362 ,  G02F1/1368 ,  G02F1/1343 ,  G02F1/1335 ,  G06F3/044 ,  G02F1/1333

CPC classification number: G06F3/0416 ,  G06F3/0412 ,  G06F3/044 ,  G09G3/20 ,  G09G3/36 ,  G09G2310/0202

Abstract: A touch detection device includes a substrate, a plurality of drive electrodes arranged on a plane parallel to the substrate and in a first region in which an image is displayed, and a plurality of touch detection electrodes configured to generate a capacitance between the touch detection electrodes and the drive electrodes. At least one touch detection electrode among the touch detection electrodes includes a first part arranged in the first region and a second part arranged in a second region adjacent to the first region. The drive electrodes are sequentially supplied with the first drive signal to detect a conducting body in contact with or close to the first region in a first touch detection mode, and the touch detection electrodes are supplied with a second drive signal to detect a conducting body in contact with or close to the second region in a second touch detection mode.

Abstract translation: 触摸检测装置包括基板，布置在平行于基板的平面上的多个驱动电极和显示图像的第一区域中的多个触摸检测电极以及在触摸检测电极之间产生电容的多个触摸检测电极 和驱动电极。 触摸检测电极中的至少一个触摸检测电极包括布置在第一区域中的第一部分和布置在与第一区域相邻的第二区域中的第二部分。 驱动电极顺序地被提供有第一驱动信号，以在第一触摸检测模式下检测与第一区域接触或接近的导电体，并且向触摸检测电极提供第二驱动信号以检测导体 在第二触摸检测模式下与第二区域接触或接近。

公开(公告)号：US09367079B2

公开(公告)日：2016-06-14

申请号：US13837676

申请日：2013-03-15

Applicant: West Virginia University

Inventor： Brandon Michael Kelly ,  Brandon David Rumberg ,  David W. Graham

IPC: G06F1/04 ,  G06F1/14 ,  G06F1/08 ,  G06F3/05 ,  G06F13/24 ,  G06F9/44 ,  H04L12/24 ,  G06F1/32 ,  H04W52/02

CPC classification number: G06F1/3293 ,  G06F1/08 ,  G06F1/10 ,  G06F1/3203 ,  G06F1/3275 ,  G06F3/05 ,  G06F9/4418 ,  G06F13/24 ,  H04L41/0816 ,  H04W52/02 ,  Y02D10/14 ,  Y02D70/00

Abstract: Aspects of a low power memory buffer are described. In one embodiment, a sampling rate of a signal is adjusted to identify extrema of a signal. An extrema pulse is generated and, in response to the extrema pulse, a time segment and potential value of the signal are stored in a memory. In other aspects, rising and falling slopes of the signal are tracked to identify a local maximum and a local minimum of the signal. In this scenario, an extrema pulse is generated for each of the local maximum and minimum, and time segment and potential values are stored for the local maximum and minimum. Generally, the storage of analog values of the signal at an adjusted sampling rate is achieved with low power, and the signal may be reconstructed at a later time.

Abstract translation: 描述低功率存储器缓冲器的方面。 在一个实施例中，调整信号的采样率以识别信号的极值。 产生极值脉冲，并且响应于极值脉冲，信号的时间段和电位值被存储在存储器中。 在其他方面，跟踪信号的上升和下降斜率以识别信号的局部最大值和局部最小值。 在这种情况下，为每个局部最大和最小值生成极值脉冲，并且为局部最大值和最小值存储时间段和电位值。 通常，以低功率实现以调整的采样率存储信号的模拟值，并且可以在稍后的时间重建信号。

公开(公告)号：US09147448B2

公开(公告)日：2015-09-29

申请号：US13834422

申请日：2013-03-15

Applicant: Infineon Technologies AG

Inventor： Tommaso Bacigalupo ,  Marcus Nuebling

IPC: G11C7/00 ,  G11C7/12 ,  G06F3/05 ,  G11C27/02 ,  G11C11/412

CPC classification number: G11C7/12 ,  G06F3/05 ,  G11C11/412 ,  G11C27/02

Abstract: A circuit arrangement is provided, including a storage circuit and an output circuit. The storage circuit is configured to provide a first output signal and a second output signal. The output circuit is configured to receive the first output signal and the second output signal and configured to provide an output signal having one of a first signal level and a second signal level, and to only switch from the first signal level to the second signal level if the difference between the first output signal and the second output signal exceeds a threshold. The circuit arrangement is configured to hold the first output signal and the second output signal independent of a difference between the first output signal and the second output signal after the switching has been carried out.

Abstract translation: 提供了一种电路装置，包括存储电路和输出电路。 存储电路被配置为提供第一输出信号和第二输出信号。 输出电路被配置为接收第一输出信号和第二输出信号，并且被配置为提供具有第一信号电平和第二信号电平之一的输出信号，并且仅从第一信号电平切换到第二信号电平 如果第一输出信号和第二输出信号之间的差超过阈值。 电路装置被配置为在执行切换之后，保持与第一输出信号和第二输出信号之间的差无关的第一输出信号和第二输出信号。

公开(公告)号：US08239158B2

公开(公告)日：2012-08-07

申请号：US12534961

申请日：2009-08-04

Applicant: Charles E. Crain, II ,  Adam H. Dewhirst ,  Robert L. Ortman

Inventor： Charles E. Crain, II ,  Adam H. Dewhirst ,  Robert L. Ortman

IPC: G06F5/01 ,  G06F3/01 ,  G06F3/05 ,  G06F3/00

CPC classification number: G06F11/273

Abstract: Various embodiments of a system and method for performing a measurement application are described herein. The system may include a host computer having a processor, and a measurement device having a programmable hardware element. The programmable hardware element may be configured to perform a loop to acquire measurement data from a physical system. The host computer may be configured to perform another loop to read the measurement data from the programmable hardware element and use the measurement data in a measurement and control algorithm. The host computer may be further configured to perform a synchronization algorithm to keep the measurement data acquisition loop performed by the programmable hardware element synchronized with the measurement and control loop performed by the host computer.

Abstract translation: 本文描述了用于执行测量应用的系统和方法的各种实施例。 该系统可以包括具有处理器的主计算机和具有可编程硬件元件的测量装置。 可编程硬件元件可以被配置为执行循环以从物理系统获取测量数据。 主机可以被配置为执行另一循环以从可编程硬件元件读取测量数据，并在测量和控制算法中使用测量数据。 主计算机还可以被配置为执行同步算法，以使由可编程硬件元件执行的测量数据采集环路与由主机执行的测量和控制回路同步。