公开(公告)号：US20030018846A1

公开(公告)日：2003-01-23

申请号：US09908678

申请日：2001-07-18

发明人： Blaise Fanning

IPC分类号： G11C005/00

CPC分类号： G11C7/1066 ,  G11C7/20 ,  G11C11/4072 ,  G11C2207/105

摘要： A system with a processor and a plurality of memories. Each memory has an individual enable pins. A logic issues parallel write operations to at least one of the memories by substantially concurrent assertion of the enable pins.

摘要翻译： 具有处理器和多个存储器的系统。 每个存储器都有一个单独的使能引脚。 逻辑通过基本上同时断言使能引脚来向至少一个存储器发出并行写入操作。

公开(公告)号：US20030018845A1

公开(公告)日：2003-01-23

申请号：US09905004

申请日：2001-07-13

发明人： Jeffery W. Janzen

IPC分类号： G11C005/00

CPC分类号： G11C7/1018 ,  G11C7/1021 ,  G11C7/103 ,  G11C8/04

摘要： An addressing scheme and associated hardware allows for two different types of access, one for reading and one for writing, to take place. A memory device constructed according to the invention comprises a plurality of arrays of memory cells. Peripheral devices are provided for reading information out of and for writing information into the plurality of memory cells. The peripheral devices include a reorder circuit responsive to certain address bits for ordering bits received from the plurality of arrays and an address sequencer for routing certain of the address bits to the reorder circuit during a read operation. The method of the present invention comprises reordering a block of n-bit words output from a memory array according to information in certain address bits before outputting at least one n-bit word from a memory device.

摘要翻译： 寻址方案和相关硬件允许进行两种不同类型的访问，一种用于阅读，一种用于写入。 根据本发明构造的存储器件包括多个存储单元阵列。 提供外部设备用于从多个存储器单元读取信息并将信息写入到多个存储器单元中。 外围设备包括响应于某些地址位的排序电路，用于排序从多个阵列接收的位;以及地址定序器，用于在读取操作期间将某些地址位路由到重排序电路。 本发明的方法包括：在从存储器件输出至少一个n位字之前，根据某些地址位中的信息重新排列从存储器阵列输出的n位字的块。

公开(公告)号：US20030012071A1

公开(公告)日：2003-01-16

申请号：US10241922

申请日：2002-09-12

发明人： Kevin Duesman

IPC分类号： G11C005/00

CPC分类号： H03K19/1736 ,  G11C5/06 ,  G11C29/48 ,  H01L23/525 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011 ,  H03K17/693 ,  H01L2924/00

摘要： A semiconductor die is provided with an internally programmable router to assign signal paths to select connection points. A switching matrix incorporating at least one antifuse is utilized to selectively route signal paths on the semiconductor die. The chips can then be used individually, for example to reconfigure chip pin assignments to operate in a plurality of different socket layouts, or where features or controls of a chip are selectively enabled or disabled. A further alternative involves programming a first chip, then stacking piggyback, or one on top of the other, the first chip onto a second chip. The contact pins are electrically coupled together, thus avoiding the need for external frames and pin rerouting schemes to form stacked chips. In the stacked chip configuration, control pins are rerouted to align with unused pins on the chip stacked against.

摘要翻译： 半导体管芯具有内部可编程的路由器以分配信号路径以选择连接点。 采用包含至少一个反熔丝的开关矩阵来选择性地路由半导体管芯上的信号路径。 然后可以单独使用芯片，例如重新配置芯片引脚分配以在多个不同的插座布局中操作，或者芯片的特征或控制被选择性地启用或禁用。 另一个替代方案涉及对第一芯片进行编程，然后将第一芯片堆叠到另一芯片上，或者将第一芯片堆叠在另一芯片上。 接触引脚电耦合在一起，从而避免了对外部框架和引脚重新布线方案的需要以形成堆叠的芯片。 在堆叠式芯片配置中，控制引脚被重新路由以与堆叠的芯片上的未使用的引脚对齐。

公开(公告)号：US20030007411A1

公开(公告)日：2003-01-09

申请号：US10184133

申请日：2002-06-26

发明人： Haruyasu Fukui ,  Ken Sumitani ,  Yasumichi Mori

IPC分类号： G11C007/00 ,  G11C005/00 ,  G11C008/00

CPC分类号： G06F13/28

摘要： A data transfer control device of the present invention includes: a command recognition section for recognizing the input control command; a first address output section for controlling an output and storage order of the data transfer addresses and the data transfer completion address based on the input control command; a first memory address storage section for storing the data transfer start address of the first memory array output from the first address output section; a second memory address storage section for storing the data transfer start address of the second memory array output from the first address output section; a third memory address storage section for storing the data transfer completion address output from the first address output section.

公开(公告)号：US20030007391A1

公开(公告)日：2003-01-09

申请号：US10190814

申请日：2002-07-08

发明人： Peter Beer ,  Thilo Schaffroth

IPC分类号： G11C005/00

CPC分类号： G11C7/18 ,  G11C7/062 ,  G11C11/4091 ,  G11C11/4097

摘要： A circuit configuration for evaluating electrical charges of memory cells in a DRAM is provided. Signal lines within the evaluation circuit cross one another in order to reduce parasitic coupling capacitances between adjacent signal lines of a memory cell array.

摘要翻译： 提供了用于评估DRAM中的存储单元的电荷的电路配置。 评估电路内的信号线彼此交叉，以减少存储单元阵列的相邻信号线之间的寄生耦合电容。

公开(公告)号：US20020196671A1

公开(公告)日：2002-12-26

申请号：US10179489

申请日：2002-06-24

发明人： Pien Chien

IPC分类号： G11C005/00 ,  G11C015/00

CPC分类号： G11C29/70 ,  G11C11/408 ,  G11C15/00 ,  G11C29/789 ,  G11C29/846

摘要： A DRAM module and a method of replacing a damaged DRAM cell in the DRAM module with a SRAM. The DRAM module has at least a non-volatile memory and a DRAM control logic circuit. In the process of replacing the damaged DRAM with the SRAM, the damaged address data is compared to DRAM address data. If the data are consistent, the address of the SRAM is used to access data. Meanwhile, the output enabling signal of the DRAM cell is turned off. It can thus assist the computer to correctly find the good DRAM cell for data access, so as to ensure a normal operation of the computer.

摘要翻译： DRAM模块和用SRAM替代DRAM模块中损坏的DRAM单元的方法。 DRAM模块至少具有非易失性存储器和DRAM控制逻辑电路。 在用SRAM替换损坏的DRAM的过程中，将损坏的地址数据与DRAM地址数据进行比较。 如果数据一致，则使用SRAM的地址来访问数据。 同时，关闭DRAM单元的输出使能信号。 因此，它可以帮助计算机正确找到用于数据访问的良好DRAM单元，以确保计算机的正常运行。

公开(公告)号：US20020196668A1

公开(公告)日：2002-12-26

申请号：US10231682

申请日：2002-08-29

申请人： Micron Technology, Inc.

发明人： Todd A. Merritt ,  Troy A. Manning

IPC分类号： G11C005/00

CPC分类号： G11C7/109 ,  G06F12/0638 ,  G06F2212/2022 ,  G11C7/1021 ,  G11C7/1024 ,  G11C7/1027 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/22 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/4096

摘要： An integrated circuit memory device is designed to perform high speed data write cycles. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. A transition of the Read/Write control line during a burst access is used to terminate the burst access and initialize the device for another burst access. Write cycle times are maximized to allow for increases in burst mode operating frequencies. Local logic gates near a nay sense amplifiers are used to control write is data drivers to provide for maximum write times without crossing current during input/output line equilibration periods. By gating global write enable signals with global equilibrate signals locally at data sense amp locations, local write cycle control signals are provided which are valid for essentially the entire cycle time minus an I/O line equilibration period in burst access memory devices. For nonburst mode memory devices such as EDO and Fast Page Mode, the write function may begin immediately following the end of the equilibration cycle to provide a maximum write time without interfering with the address setup time of the next access cycle.

摘要翻译： 集成电路存储器件被设计为执行高速数据写入周期。 地址选通信号用于锁存第一个地址。 在突发访问周期期间，地址在设备内部增加，并具有额外的地址选通转换。 只有在每次突发访问开始时才需要新的内存地址。 读/写命令每次突发存取发出一次，无需在器件周期频率下切换读/写控制线。 在脉冲串访问期间读/写控制线的转换用于终止脉冲串访问并初始化该设备以进行另一脉冲串访问。 写周期时间最大化以允许突发模式工作频率的增加。 靠近读出放大器的本地逻辑门用于控制写入数据驱动器，以提供最大写入时间，而不会在输入/输出线路平衡周期期间交叉电流。 通过在数据检测放大器位置局部地选通具有全局平衡信号的全局写使能信号，提供本地写周期控制信号，其基本上对整个周期时间有效，减去突发存取存储器件中的I / O线平衡周期。 对于诸如EDO和快速页面模式的非突发模式存储器件，写入功能可以在平衡周期结束后立即开始，以提供最大写入时间，而不会干扰下一个访问周期的地址建立时间。

公开(公告)号：US20020191472A1

公开(公告)日：2002-12-19

申请号：US09987837

申请日：2001-11-16

申请人： Mitsubishi Denki Kabushiki Kaisha

发明人： Takeo Okamoto ,  Tadaaki Yamauchi ,  Junko Matsumoto

IPC分类号： G11C005/00

CPC分类号： G11C5/147

摘要： In a low power consumption mode, an internal power supply circuit produces an internal power supply voltage by electrically coupling an internal power supply line to either an external power supply line or a ground line through a transistor. Accordingly, in the low power consumption mode, supply of an operating current to a reference voltage generation circuit, a buffer circuit, an internal power supply voltage generation circuit and a voltage booster circuit is discontinued, allowing for reduction in power consumption of the internal power supply circuit itself.

摘要翻译： 在低功耗模式中，内部电源电路通过将内部电源线通过晶体管电连接到外部电源线或接地线来产生内部电源电压。 因此，在低功耗模式中，停止向参考电压产生电路，缓冲电路，内部电源电压产生电路和升压电路的供电，允许内部电力的功耗降低 供电电路本身。

公开(公告)号：US20020181311A1

公开(公告)日：2002-12-05

申请号：US09986873

申请日：2001-11-13

申请人： Mitsubishi Denki Kabushiki Kaisha

发明人： Shigenori Miyauchi

IPC分类号： G11C005/00

CPC分类号： G06F3/0625 ,  G06F1/3275 ,  G06F3/0659 ,  G06F3/0688 ,  G11C5/143 ,  G11C16/30 ,  Y02D10/14 ,  Y02D10/154

摘要： A semiconductor memory unit which includes a plurality of nonvolatile memories for storing data and is operable at a plurality of source voltages, comprising: a voltage detector for detecting an input voltage inputted to the semiconductor memory unit from the source voltages; and a central processing unit (CPU) which sets a maximum permissible current consumption value of the semiconductor memory unit on the basis of the input voltage and controls the number of the nonvolatile memories operated at a time such that a current consumption value of the semiconductor memory unit does not exceed the maximum permissible current consumption value.

摘要翻译： 一种半导体存储单元，包括用于存储数据的多个非易失性存储器，并且可在多个源电压下操作，包括：电压检测器，用于根据源电压检测输入到半导体存储器单元的输入电压; 以及中央处理单元（CPU），其基于输入电压设置半导体存储器单元的最大允许电流消耗值，并且控制一次操作的非易失性存储器的数量，使得半导体存储器的电流消耗值 单位不超过最大允许电流消耗值。

公开(公告)号：US20020181290A1

公开(公告)日：2002-12-05

申请号：US10157726

申请日：2002-05-29

发明人： Robert Feurle ,  Paul Schmolz ,  Jean-Marc Dortu ,  Andreas Tauber

IPC分类号： G11C005/00

CPC分类号： G11C7/106 ,  G11C7/1051 ,  G11C7/1066

摘要： A data output interface, in particular for semiconductor memories, provides a plurality of output drivers for providing data output signals in a manner dependent on a read command and a clock signal. In order to signal to a microprocessor that can be connected to the data output that data are provided, a data provision signal is additionally provided by a further output driver. The arrangement described can preferably be used for DDR-SDRAMs and enables particularly high clock frequencies.

摘要翻译： 特别是半导体存储器的数据输出接口提供多个输出驱动器，用于以取决于读指令和时钟信号的方式提供数据输出信号。 为了向可以连接到数据输出端的微处理器发出信号，另外还有一个输出驱动器提供数据提供信号。 所描述的布置可以优选地用于DDR-SDRAM并且能够实现特别高的时钟频率。