公开(公告)号：US20030142547A1

公开(公告)日：2003-07-31

申请号：US10331106

申请日：2002-12-27

Applicant: STMicroelectronics S.r.I.

Inventor： Rino Micheloni ,  Ilaria Motta

IPC: G11C011/34

CPC classification number: G11C16/30

Abstract: A method and a circuit are for regulating the source terminal voltage of a non-volatile memory cell during the cell programming and/or reading phases. The method includes a phase of locally regulating the voltage value and includes comparing the source current of the cell array with a reference current. A fraction of the source current is converted to a voltage and compared with a voltage generated from a memory cell acting as a reference and being programmed to the distribution with the highest current levels. The comparison may be used for controlling a current generator to inject, into the source terminal, the current necessary to keep the predetermined voltage thereof at a constant value.

Abstract translation: 一种方法和电路用于在单元编程和/或读取阶段期间调节非易失性存储单元的源极端子电压。 该方法包括局部调节电压值的相位，并且包括将电池阵列的源电流与参考电流进行比较。 将源电流的一部分转换成电压，并将其与作为参考的存储器单元产生的电压进行比较，并将其编程为具有最高电流电平的分布。 比较可以用于控制电流发生器向源极端子注入将其预定电压保持在恒定值所需的电流。

公开(公告)号：US20030122693A1

公开(公告)日：2003-07-03

申请号：US10325707

申请日：2002-12-20

Applicant: STMicroelectronics S.r.I.

Inventor： Luigi Pascucci

IPC: H03M005/00

CPC classification number: H03M5/00

Abstract: A binary encoding circuit is for converting at least first and second binary input signals into an output code that includes at least first and second binary output signals. The circuit may include at least one first selection circuit and at least one second selection circuit that are interconnected and comprise transistors that can be activated/deactivated, i.e. made to conduct/not conduct, according to the binary input signals. The circuit makes it possible to generate a binary code that represents the binary number of the binary input signals that are simultaneously asserted. The encoding circuit can act as a static counter, for example.

Abstract translation: 二进制编码电路用于将至少第一和第二二进制输入信号转换成包括至少第一和第二二进制输出信号的输出代码。 电路可以包括互连的至少一个第一选择电路和至少一个第二选择电路，并且包括可以被激活/去激活的晶体管，即根据二进制输入信号导通/不导通的晶体管。 该电路使得可以生成表示同时被断言的二进制输入信号的二进制数的二进制代码。 例如，编码电路可以用作静态计数器。

公开(公告)号：US20030107825A1

公开(公告)日：2003-06-12

申请号：US10171453

申请日：2002-06-13

Applicant: STMicroelectronics S.r.I. ,  STMicroelectronics Limited

Inventor： Pierangelo Magni ,  Francesco Sala ,  Eric Christison ,  Andrea Giovanni Cigada

IPC: G02B007/02

CPC classification number: G02B7/022 ,  G02B7/04 ,  H01L31/0203 ,  H01L31/02325 ,  H04N5/2253 ,  H04N5/2254

Abstract: An image-detecting device including: a body housing a sensor; a first supporting element, rigidly coupled with the body and defining a seat; and an objective including at least one optical unit having an optical axis. The seat forms a guide portion engaging directly and slidably an alignment portion formed by said optical unit to keep the optical axis orthogonal to the sensor.

Abstract translation: 一种图像检测装置，包括：容纳传感器的主体; 第一支撑元件，与主体刚性联接并且限定座椅; 以及包括具有光轴的至少一个光学单元的目标。 所述座部形成与所述光学单元形成的对准部分直接且可滑动地接合以使光轴正交于所述传感器的引导部。

公开(公告)号：US20030101410A1

公开(公告)日：2003-05-29

申请号：US10176968

申请日：2002-06-21

Applicant: STMicroelectronics S.r.I

Inventor： Giorgio Betti ,  Filippo Brenna ,  Angelo Dati ,  Augusto Rossi ,  Luca Reggiani

IPC: H03M013/00 ,  H03M013/03

CPC classification number: G11B20/10296 ,  G11B20/10009 ,  G11B20/1833

Abstract: A method and apparatus for detecting and correcting errors in a magnetic recording channel of a mass storage system that combines a Soft Output Viterbi Algorithm SOVA, which has the capability of detecting the reliability of a discrete, equalized signal, and a post processor, which has the capability of detecting specific error events in said discrete, equalized signal, so as to correct error events and to generate an output bit stream.

Abstract translation: 一种用于检测和校正大容量存储系统的磁记录通道中的错误的方法和装置，其组合具有检测离散均衡信号的可靠性的能力的软输出维特比算法SOVA和后处理器，后处理器具有 在所述离散的均衡信号中检测特定错误事件的能力，以便校正错误事件并产生输出比特流。

公开(公告)号：US20030080781A1

公开(公告)日：2003-05-01

申请号：US10282487

申请日：2002-10-28

Applicant: STMICROELECTRONICS S.r.I.

Inventor： Giacomo Curatolo ,  Ignazio Martines ,  Davide Torrisi

IPC: H03K019/094

CPC classification number: H03K19/00361 ,  H03K17/167

Abstract: An output buffer for causing a voltage (Vout) of an integrated circuit output line (OUT,OUT13 PAD) to switch from a voltage of a first voltage line (VDD) to a voltage of a second voltage line (GND) and vice versa, comprises a current path switch circuit (111a,111b) activatable for causing a prescribed current (Is) to constantly flow between the first and second voltage lines during a time between two successive switchings of the output line, and for causing the prescribed current to be deviated (Ic1) to the output line during at least an initial phase of an output line switching from the first voltage line voltage to the second voltage line voltage or vice versa. A current delivered by the first and second voltage lines is thus kept substantially constant in the output line switching. In this way, the time derivative of the current flowing between the first and the second voltage lines is kept small and low switching noise is induced.

Abstract translation: 一种用于使集成电路输出线（OUT，OUT13 PAD）的电压（Vout）从第一电压线（VDD）的电压切换到第二电压线（GND）的电压的输出缓冲器，反之亦然， 包括电流路径切换电路（111a，111b），其能够在输出线的两次连续切换之间的时间内使规定电流（Is）恒定地在第一和第二电压线之间流动，并且使规定电流为 在从第一电压线电压切换到第二电压线电压的输出线的至少初始相位期间偏离（Ic1）到输出线，反之亦然。 因此，输出线切换中由第一和第二电压线传递的电流基本保持恒定。 以这种方式，在第一和第二电压线之间流动的电流的时间导数保持较小，并且引起低的开关噪声。

公开(公告)号：US20030075739A1

公开(公告)日：2003-04-24

申请号：US10251907

申请日：2002-09-20

Applicant: STMICROELECTRONICS S.r.I.

Inventor： Antonino Schillaci ,  Paola Maria Ponzio

IPC: H01L029/76

CPC classification number: H01L29/7802 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66712 ,  Y10S438/981

Abstract: A MOS semiconductor device formed on a substrate of a first conductivity type is provided. The device includes active zones for elementary active elements, and at least one inactive zone suitable for electric signal input or output. The substrate is connected with the drain terminal of the device, and at least one of the elementary active elements includes a body region of a second conductivity type that is connected with the source terminal of the device. The at least one inactive zone includes a semiconductor region of the second conductivity type formed in the substrate and adjacent a surface of the substrate, a conductive layer located over the semiconductor region, and a silicon oxide layer located between the semiconductor region and the conductive layer. The silicon oxide layer has alternating first zones and second zones that are contiguous to each other, with the first zones having a greater thickness than the second zones.

Abstract translation: 提供了形成在第一导电类型的衬底上的MOS半导体器件。 该装置包括用于基本有源元件的活动区域和至少一个适用于电信号输入或输出的非活动区域。 衬底与器件的漏极端子连接，并且至少一个基本有源元件包括与器件的源极端子连接的第二导电类型的体区。 所述至少一个非活性区域包括形成在所述衬底中并且邻近所述衬底的表面的第二导电类型的半导体区域，位于所述半导体区域上方的导电层以及位于所述半导体区域和所述导电层之间的氧化硅层 。 氧化硅层具有彼此邻接的交替的第一区和第二区，第一区具有比第二区更大的厚度。

公开(公告)号：US20030067036A1

公开(公告)日：2003-04-10

申请号：US10237553

申请日：2002-09-09

Applicant: STMicroelectronics S.r.I.

Inventor： Riccardo Depetro ,  Anna Ponza ,  Antonio Gallerano

IPC: H01L021/336 ,  H01L029/76 ,  H01L029/94 ,  H01L031/062 ,  H01L031/119 ,  H01L031/113

CPC classification number: H01L29/7816 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/4238

Abstract: An MOS electronic device is formed to reduce drain/gate capacity and to increase cutoff frequency. The device includes a field insulating layer that covers a drain region, delimits an active area with an opening, houses a body region in the active area, and houses a source region in the body region. A portion of the body region between drain and source regions forms a channel region. A polycrystalline silicon structure extends along the edge of the opening, partially on the field insulating and active layers. The polycrystalline silicon structure includes a gate region extending along a first portion of the edge on the channel region and partially surrounding the source region and a non-operative region extending along a second portion of the edge, electrically insulated and at a distance from the gate region.

Abstract translation: 形成MOS电子器件以减少漏极/栅极容量并增加截止频率。 该器件包括覆盖漏极区域的场绝缘层，限定具有开口的有源区域，在有源区域中容纳主体区域，并且容纳主体区域中的源极区域。 漏极和源极区域之间的体区的一部分形成沟道区。 多晶硅结构沿着开口的边缘延伸，部分地在场绝缘层和有源层上延伸。 多晶硅结构包括沿沟道区域上的边缘的第一部分延伸并且部分地围绕源极区域的栅极区域和沿边缘的第二部分延伸的非操作区域，电绝缘并且距离栅极一定距离 地区。

公开(公告)号：US20020185827A1

公开(公告)日：2002-12-12

申请号：US10115887

申请日：2002-04-03

Applicant: STMicroelectronics S.r.I.

Inventor： Riccardo Caponetto ,  Olga Diamante ,  Antonio Risitano ,  Giovanna Fargione ,  Domenico Tringali

IPC: B60G017/01

CPC classification number: B60G17/018 ,  B60G2400/102 ,  B60G2400/252 ,  B60G2500/10 ,  B60G2600/1879 ,  B60G2800/70 ,  Y10S706/90

Abstract: A method for controlling a vehicle semi-active suspension system comprising at least one suspension, providing for: detecting vehicle dynamic quantities during the vehicle ride; using the detected dynamic quantities, determining an index of ride comfort and an index of roadholding; applying a weight factor to the index of ride comfort and to the index of roadholding and, based on a Sky Hook control model, determining a target damping force characteristics for the at least one suspension of the suspension system; controlling the at least one suspension to put the respective damping force characteristics in accordance with the calculated target damping force characteristics. The weight factor is calculated dynamically during the vehicle ride, by means of a fuzzy calculation on the detected vehicle dynamic quantities.

Abstract translation: 一种用于控制包括至少一个悬架的车辆半主动悬架系统的方法，提供：在车辆行驶期间检测车辆动态量; 使用检测到的动态量，确定乘坐舒适性指标和道路保持指数; 将重量因子应用于乘坐舒适度指数和道路保持指数，并且基于Sky Hook控制模型，确定悬架系统的至少一个悬架的目标阻尼力特性; 控制所述至少一个悬架以根据所计算的目标阻尼力特性来设置相应的阻尼力特性。 通过对检测到的车辆动态量的模糊计算，在车辆行驶期间动态计算加权因子。

公开(公告)号：US20020131303A1

公开(公告)日：2002-09-19

申请号：US10068560

申请日：2002-02-05

Applicant: STMicroelectronics S.r.I.

Inventor： Ignazio Martines ,  Luigi Buono

IPC: G11C016/04

CPC classification number: G11C16/30 ,  G11C5/145

Abstract: A charge pump for a nonvolatile memory, having a clock generator circuit supplying an output clock signal; a phase generator circuit receiving the output clock signal, and supplying phase signals; and a voltage booster circuit receiving a supply voltage supplied from outside to the nonvolatile memory and the aforesaid phase signals, and supplying a read voltage higher than the supply voltage. The clock generator circuit includes a comparator receiving the read voltage and a reference voltage, and supplying a selection signal indicating the outcome of the comparison between the read and reference voltages; and a multiplexer receiving a first input clock signal having a pre-set frequency, a second input clock signal having a frequency correlated to the transition frequency of the addresses supplied to the nonvolatile memory, and the selection signal, and supplying the aforesaid output clock signal.

Abstract translation: 一种用于非易失性存储器的电荷泵，具有提供输出时钟信号的时钟发生器电路; 接收所述输出时钟信号并提供相位信号的相位发生器电路; 以及接收从外部向非易失性存储器提供的电源电压和上述相位信号的升压电路，并提供高于电源电压的读取电压。 时钟发生器电路包括：比较器，接收读取电压和参考电压，并提供指示读取和参考电压之间的比较结果的选择信号; 以及多路复用器，其接收具有预置频率的第一输入时钟信号，具有与提供给非易失性存储器的地址的转换频率相关的频率的第二输入时钟信号和所述选择信号，以及提供所述输出时钟信号 。

公开(公告)号：US20020127761A1

公开(公告)日：2002-09-12

申请号：US10037484

申请日：2001-12-19

Applicant: STMicroelectronics S.r.I.

Inventor： Marta Mottura ,  Alessandra Fischetti ,  Marco Ferrera ,  Bernardino Zerbini ,  Mauro Bombonati

IPC: H01L021/00

CPC classification number: H01L21/2007 ,  H01L21/76256

Abstract: A process for manufacturing components in a multi-layer wafer, including the steps of: providing a multi-layer wafer comprising a first semiconductor material layer, a second semiconductor material layer (, and a dielectric material layer arranged between the first and the second semiconductor material layer; and removing the first semiconductor material layer initially by mechanically thinning the first semiconductor material layer, so as to form a residual conductive layer, and subsequently by chemically removing the residual conductive layer. In one application, the multi-layer wafer is bonded to a first wafer of semiconductor material, with the second semiconductor material layer facing the first wafer, after micro-electromechanical structures have been formed in the second semiconductor material layer of the multi-layer wafer.

Abstract translation: 一种用于制造多层晶片中的部件的方法，包括以下步骤：提供包括第一半导体材料层，第二半导体材料层（以及布置在第一和第二半导体之间的介电材料层）的多层晶片 最初通过机械稀化第一半导体材料层去除第一半导体材料层，从而形成残留的导电层，随后通过化学去除残留的导电层，在一个应用中，多层晶片被粘合 在多层晶片的第二半导体材料层中形成微机电结构之后，将第二半导体材料层面向第一晶片的半导体材料的第一晶片。