公开(公告)号：US20250097306A1

公开(公告)日：2025-03-20

申请号：US18894452

申请日：2024-09-24

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Patrick Bohan ,  Kshitij Arun Doshi ,  Brinda Ganesh ,  Andrew J. Herdrich ,  Monica Kenguva ,  Karthik Kumar ,  Patrick G. Kutch ,  Felipe Pastor Beneyto ,  Rashmin Patel ,  Suraj Prabhakaran ,  Ned M. Smith ,  Petar Torre ,  Alexander Vul

IPC: H04L67/148 ,  G06F9/48 ,  H04L41/5003 ,  H04L41/5019 ,  H04L43/0811 ,  H04L47/70 ,  H04L67/00 ,  H04L67/10 ,  H04W4/40 ,  H04W4/70

Abstract: An architecture to perform resource management among multiple network nodes and associated resources is disclosed. Example resource management techniques include those relating to: proactive reservation of edge computing resources; deadline-driven resource allocation; speculative edge QOS pre-allocation; and automatic QoS migration across edge computing nodes. In a specific example, a technique for service migration includes: identifying a service operated with computing resources in an edge computing system, involving computing capabilities for a connected edge device with an identified service level; identifying a mobility condition for the service, based on a change in network connectivity with the connected edge device; and performing a migration of the service to another edge computing system based on the identified mobility condition, to enable the service to be continued at the second edge computing apparatus to provide computing capabilities for the connected edge device with the identified service level.

公开(公告)号：US20250097249A1

公开(公告)日：2025-03-20

申请号：US18965769

申请日：2024-12-02

Applicant: Intel Corporation

Inventor： Omer Ben-Shalom ,  Yoni Kahana ,  Yaron Klein ,  Ilil Blum Shem-Tov ,  Dan Horovitz

IPC: H04L9/40

Abstract: An example apparatus includes interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to interface circuitry to obtain a pre-trained detection model, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to tune the pre-trained detection model based on first local behavior data and execute the tuned detection model to detect an anomaly in second local behavior data associated with the apparatus.

公开(公告)号：US20250097120A1

公开(公告)日：2025-03-20

申请号：US18966019

申请日：2024-12-02

Applicant: Intel Corporation

Inventor： Francesc GUIM BERNAT ,  Suraj PRABHAKARAN ,  Kshitij A. DOSHI ,  Brinda GANESH ,  Timothy VERRALL

IPC: H04L41/16 ,  G06N3/04 ,  G06N5/04 ,  H04L41/0816 ,  H04L41/5009 ,  H04L41/5019 ,  H04L41/5051

Abstract: Examples include techniques for artificial intelligence (AI) capabilities at a network switch. These examples include receiving a request to register a neural network for loading to an inference resource located at the network switch and loading the neural network based on information included in the request to support an AI service to be provided by users requesting the AI service.

公开(公告)号：US20250096052A1

公开(公告)日：2025-03-20

申请号：US18469674

申请日：2023-09-19

Applicant: Intel Corporation

Inventor： Mohamed R. Saber ,  Hanyu Song ,  Fanyi Zhu ,  Bai Nie ,  Srinivas V. Pietambaram ,  Deniz Turan ,  Yonggang Li ,  Naiya Soetan-Dodd ,  Shuren Qu

IPC: H01L23/15 ,  H01L21/48 ,  H01L23/00 ,  H01L23/48 ,  H01L25/065

Abstract: Microelectronic assemblies with glass cores that have undergone localized thermal healing and/or localized doping in regions adjacent to glass surface are disclosed. In one example, a microelectronic assembly includes a glass core having a first face, an opposing second face, a sidewall extending between the first face and the second face, a surface region, and a bulk region, where the surface region is a portion of the glass core that starts at a surface of the first face, the second face, or the sidewall and extends from the surface into the glass core by a total depth of up to about 50 micron, the bulk region is a portion of the glass core further away from the surface than the surface region, and a density of the surface region is higher than a density of the bulk region, e.g., at least about 5% higher or at least about 7.5% higher.

公开(公告)号：US20250093413A1

公开(公告)日：2025-03-20

申请号：US18963838

申请日：2024-11-29

Applicant: Intel Corporation

Inventor： Zhen ZHOU ,  Renzhi LIU ,  Jong-Ru GUO ,  Kenneth P. FOUST ,  Jason A. MIX ,  Kai XIAO ,  Zuoguo WU ,  Daqiao DU

IPC: G01R31/302 ,  G01R31/28 ,  G01R31/303 ,  H01P3/08 ,  H01Q9/16 ,  H04B5/48

Abstract: A high volume manufacturing (HVM) test system including a test device defining an opening configured to receive a package under test, the test device including an external access agent (EAA) including: a first leaky surface wave launcher for near field wireless communication, the first leaky surface wave launcher configured to wirelessly provide sideband signals to and wirelessly receive the sideband signals from a silicon package agent physically positioned in a separate package as the EAA; and a first transceiver electrically coupled to the first leaky surface wave launcher, the first transceiver configured to: process the sideband signals received by the first leaky surface wave launcher; and generate the sideband signals for wireless transmission by the first leaky surface wave launcher.

公开(公告)号：US12255897B2

公开(公告)日：2025-03-18

申请号：US18478692

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Hong C. Li ,  John B. Vicente ,  Prashant Dewan

IPC: H04L9/40 ,  G06F21/51 ,  G06F21/53 ,  H04L67/02

Abstract: Systems and methods may provide for receiving web content and determining a trust level associated with the web content. Additionally, the web content may be mapped to an execution environment based at least in part on the trust level. In one example, the web content is stored to a trust level specific data container.

公开(公告)号：US12255648B2

公开(公告)日：2025-03-18

申请号：US17350577

申请日：2021-06-17

Applicant: Intel Corporation

Inventor： Archanna Srinivasan ,  Ravi Gutala ,  Scott Weber ,  Aravind Dasu ,  Mahesh Iyer ,  Eriko Nurvitadhi

IPC: H03K19/17788 ,  H03K19/17728 ,  H03K19/17792

Abstract: A circuit system includes a first integrated circuit die having a first group of circuits configured to perform a first set of operations. The circuit system also includes a second integrated circuit die having a second group of circuits configured to start performing a second set of operations with a delay after the first group of circuits starts performing the first set of operations to reduce power supply voltage droop. The operations performed by the first and second groups of circuits can be interleaved with a fixed or a variable delay. Logic circuits can be partitioned into the first and the second groups of circuits based on predicted switching activity of the logic circuits. Decoupling capacitors in integrated circuit dies can be coupled together to reduce droop in a supply voltage during a high current event.

公开(公告)号：US12255158B2

公开(公告)日：2025-03-18

申请号：US16911543

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Neelam Prabhu Gaunkar ,  Georgios Dogiamis ,  Telesphor Kamgaing ,  Diego Correas-Serrano ,  Henning Braunisch

IPC: H01L23/66 ,  H01L23/498 ,  H01P3/00 ,  H01P3/08

Abstract: Disclosed herein are components for millimeter-wave communication, as well as related methods and systems.

公开(公告)号：US12255137B2

公开(公告)日：2025-03-18

申请号：US18419015

申请日：2024-01-22

Applicant: Intel Corporation

Inventor： Ehren Mannebach ,  Aaron Lilak ,  Hui Jae Yoo ,  Patrick Morrow ,  Anh Phan ,  Willy Rachmady ,  Cheng-Ying Huang ,  Gilbert Dewey ,  Rishabh Mehandru

IPC: H01L23/522 ,  H01L21/8234 ,  H01L25/16 ,  H01L29/06

Abstract: Embodiments disclosed herein include electronic systems with vias that include a horizontal and vertical portion in order to provide interconnects to stacked components, and methods of forming such systems. In an embodiment, an electronic system comprises a board, a package substrate electrically coupled to the board, and a die electrically coupled to the package substrate. In an embodiment the die comprises a stack of components, and a via adjacent to the stack of components, wherein the via comprises a vertical portion and a horizontal portion.

公开(公告)号：US12254341B2

公开(公告)日：2025-03-18

申请号：US18353694

申请日：2023-07-17

Applicant: Intel Corporation

Inventor： Ravi L. Sahita ,  Tin-Cheung Kung ,  Vedvyas Shanbhogue ,  Barry E. Huntley ,  Arie Aharon

IPC: G06F9/455 ,  G06F9/50 ,  H04L9/06

Abstract: Implementations describe a computing system that implements a plurality of virtual machines inside a trust domain (TD), enabled via a secure arbitration mode (SEAM) of the processor. A processor includes one or more registers to store a SEAM range of memory, a TD key identifier of a TD private encryption key. The processor is capable of initializing a trust domain resource manager (TDRM) to manage the TD, and a virtual machine monitor within the TD to manage the plurality of virtual machines therein. The processor is further capable of exclusively associating a plurality of memory pages with the TD, wherein the plurality of memory pages associated with the TD is encrypted with a TD private encryption key inaccessible to the TDRM. The processor is further capable of using the SEAM range of memory, inaccessible to the TDRM, to provide isolation between the TDRM and the plurality of virtual machines.