公开(公告)号：US5926713A

公开(公告)日：1999-07-20

申请号：US923322

申请日：1997-09-04

申请人： Fred N. Hause ,  Basab Bandyopadhyay ,  H. Jim Fulford, Jr. ,  Robert Dawson ,  Mark W. Michael ,  William S. Brennan

发明人： Fred N. Hause ,  Basab Bandyopadhyay ,  H. Jim Fulford, Jr. ,  Robert Dawson ,  Mark W. Michael ,  William S. Brennan

IPC分类号： H01L21/3105 ,  H01L21/336 ,  H01L21/762

CPC分类号： H01L29/66712 ,  H01L21/31053 ,  H01L21/76229

摘要： An isolation technique is provided for improving the overall planarity of trench isolation regions relative to adjacent silicon mesas. The isolation process results in a spaced plurality of silicon risers formed in wide isolation regions. The space between silicon risers are ideally suited for optimal fill of a dielectric deposited across the semiconductor topography, i.e., across and between the silicon risers formed between active areas. The silicon risers, and optimally dimensioned trenches extending between the risers, enhance the planarity of the deposited dielectric. The deposited dielectric upper surface includes recesses of minimal elevational disparity, wherein the recesses are closely spaced in alignment directly above the trenches formed between silicon risers. The recesses can be readily removed by a chemical-mechanical polishing step with minimal deformity to the polishing pad, resulting in global planarization of the dielectric upper surface.

摘要翻译： 提供隔离技术用于改善沟槽隔离区域相对于相邻硅台面的整体平面度。 分离过程导致在宽隔离区域中形成间隔开的多个硅提升管。 硅提升管之间的空间理想地适用于跨半导体形貌沉积的电介质的最佳填充，即在活性区域之间形成的硅提升板之间和之间。 硅立管和在立管之间延伸的最佳尺寸的沟槽增强了沉积的电介质的平面性。 沉积的电介质上表面包括具有最小高度差异的凹槽，其中凹槽在硅立管之间形成的沟槽的正上方紧密间隔开。 可以通过化学机械抛光步骤容易地去除凹部，对抛光垫具有最小的变形，导致电介质上表面的全局平坦化。

公开(公告)号：US5924008A

公开(公告)日：1999-07-13

申请号：US942248

申请日：1997-10-01

申请人： Mark W. Michael ,  Robert Dawson ,  Basab Bandyopadhyay ,  H. Jim Fulford, Jr. ,  Fred N. Hause ,  William S. Brennan

发明人： Mark W. Michael ,  Robert Dawson ,  Basab Bandyopadhyay ,  H. Jim Fulford, Jr. ,  Fred N. Hause ,  William S. Brennan

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11 ,  H01L21/4763

CPC分类号： H01L23/5222 ,  H01L21/76895 ,  H01L23/5286 ,  H01L27/11 ,  H01L2924/0002

摘要： An integrated circuit is provided having an improved interconnect structure. The interconnect structure includes a power-coupled local interconnect which is always retained at VDD or VSS (i.e., ground) level. The local interconnect resides a dielectric-spaced distance below critical runs of overlying interconnect. The powered local interconnect serves to sink noise transients from the critical conductors to ensure that circuits connected to the conductors do not inoperably function. Accordingly, the local interconnect extends along a substantial portion of the conductor length, and is either wider or narrower than the conductor under which it extends. The local interconnect can either be polysilicon, doped polysilicon, polycide, refractory metal silicide, or multi-level refractory metal.

摘要翻译： 提供具有改进的互连结构的集成电路。 互连结构包括总是保持在VDD或VSS（即接地）电平的功率耦合局部互连。 局部互连在上覆互连的关键运行之下存在介电间隔距离。 有源局部互连用于吸收临界导体的噪声瞬变，以确保连接到导体的电路不起作用。 因此，局部互连沿着导体长度的大部分延伸，并且比其延伸的导体更宽或更窄。 局部互连可以是多晶硅，掺杂多晶硅，多晶硅，难熔金属硅化物或多层难熔金属。

公开(公告)号：US5885887A

公开(公告)日：1999-03-23

申请号：US847752

申请日：1997-04-21

申请人： Frederick N. Hause ,  Robert Dawson ,  H. Jim Fulford Jr. ,  Mark I. Gardner ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

发明人： Frederick N. Hause ,  Robert Dawson ,  H. Jim Fulford Jr. ,  Mark I. Gardner ,  Mark W. Michael ,  Bradley T. Moore ,  Derick J. Wristers

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/423 ,  H01L21/38

CPC分类号： H01L29/6659 ,  H01L21/28114 ,  H01L21/823842 ,  H01L29/42376

摘要： A method of making an IGFET with a selectively doped multilevel polysilicon gate that includes upper and lower polysilicon gate levels is disclosed. The method includes providing a semiconductor substrate with an active region, forming a gate insulator on the active region, forming a a lower polysilicon layer on the gate insulator, forming a first masking layer over the lower polysilicon layer, etching the lower polysilicon layer through openings in the first masking layer using the first masking layer as an etch mask for a portion of the lower polysilicon layer that forms the lower polysilicon gate level over the active region, removing the first masking layer, forming the upper polysilicon gate level on the lower polysilicon gate level after removing the first masking layer, introducing a dopant into the upper polysilicon gate level without introducing the dopant into the substrate, diffusing the dopant from the upper polysilicon gate level into the lower polysilicon gate level, and forming a source and drain in the active region. Advantageously, the lower polysilicon gate level has both an accurately defined length to provide the desired channel length and a well-controlled doping concentration to provide the desired threshold voltage.

摘要翻译： 公开了一种制造具有选择性掺杂多电平多晶硅栅极的IGFET的方法，其包括上和下多晶硅栅极电平。 该方法包括提供具有有源区的半导体衬底，在有源区上形成栅极绝缘体，在栅极绝缘体上形成下部多晶硅层，在下部多晶硅层上形成第一掩蔽层，通过下部多晶硅层的开口蚀刻下部多晶硅层 所述第一掩模层使用所述第一掩模层作为用于在所述有源区上形成所述下多晶硅栅极电平的所述下多晶硅层的一部分的蚀刻掩模，去除所述第一掩模层，在所述下多晶硅栅极上形成所述上多晶硅栅极电平 在去除第一掩模层之后，将掺杂剂引入上多晶硅栅极级，而不将掺杂剂引入衬底中，将掺杂剂从上多晶硅栅极级扩散到下多晶硅栅极电平，并在活性层中形成源极和漏极 地区。 有利地，下多晶硅栅极电平具有精确限定的长度以提供期望的沟道长度和良好控制的掺杂浓度以提供期望的阈值电压。

公开(公告)号：US5851913A

公开(公告)日：1998-12-22

申请号：US655246

申请日：1996-06-05

申请人： William S. Brennan ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Fred N. Hause ,  Basab Bandyopadhyay ,  Mark W. Michael

发明人： William S. Brennan ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Fred N. Hause ,  Basab Bandyopadhyay ,  Mark W. Michael

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/768 ,  H01L21/76807

摘要： A multilevel interconnect structure is provided. The multilevel interconnect structure includes two, three or more levels of conductors formed according to at least two exemplary embodiments. According to one embodiment, the contact structure which links conductors on one level to an underlying level is formed by a single via etch step followed by a fill step separate from a fill step used in filling the via. In this embodiment, the via is filled with a conductive material which forms a plug separate from the material used in forming the interconnect. In another exemplary embodiment, the step used in filling the via can be the same as that used in forming the interconnect. In either instance, a via is formed through a first dielectric to underlying conductors. A second dielectric is patterned upon the first dielectric and serves to laterally bound the fill material used in producing the overlying interconnect. Regardless of the process sequence chosen, the interlevel dielectric structure is left substantially planar in readiness for subsequent interconnect levels dielectically deposited thereon.

摘要翻译： 提供了多层互连结构。 多层互连结构包括根据至少两个示例性实施例形成的两层，三层或更多级的导体。 根据一个实施例，通过单个通孔蚀刻步骤形成将一个层上的导体连接到下层的接触结构，随后是与用于填充通孔的填充步骤分离的填充步骤。 在该实施例中，通孔填充导电材料，该导电材料形成与用于形成互连件的材料分开的插头。 在另一个示例性实施例中，用于填充通孔的步骤可以与在形成互连中使用的步骤相同。 在任一情况下，通孔通过第一电介质形成到下面的导体。 在第一电介质上构图第二电介质，并且用于横向地限制用于制造上覆互连的填充材料。 不管选择的工艺顺序如何，层间电介质结构留在基本上平坦的准备中，用于介于其上的后续互连层。

公开(公告)号：US5851889A

公开(公告)日：1998-12-22

申请号：US792714

申请日：1997-01-30

申请人： Mark W. Michael ,  Robert Dawson

发明人： Mark W. Michael ,  Robert Dawson

IPC分类号： H01L21/28 ,  H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/28035 ,  H01L21/823842

摘要： A semiconductor fabrication process is presented which optimizes the position of impurities within a gate conductor a the source/drain straddling the gate conductor. Optimal positioned is achieved by using separate implants of different energies depending upon whether the gate conductor connotes a PMOS or NMOS transistor. A layer of polysilicon used to form the gate conductor is doped before patterning so that the source and drain regions are protected. A low energy implant is performed when implanting a fast diffuser such as boron, and a high energy implant is performed when implanting a slow diffuser like arsenic. This enables optimum positioning of the impurities throughout the gate conductor cross-section after heat cycles are applied. Fast diffusers are initially placed far from the bottom surface of the polysilicon, and diffuse near the bottom surface of the polysilicon when heat is applied. Slow diffusers are initially placed closer to the bottom surface of the polysilicon, since they do not diffuse as readily. The source and drain regions are implanted using a very low energy implant, separately from the polysilicon implants, to produce a desirable shallow source and drain region within the semiconductor substrate.

摘要翻译： 提出了一种半导体制造工艺，其优化栅极导体内杂质的位置，栅极导体中跨越栅极导体的源极/漏极。 取决于栅极导体是指PMOS还是NMOS晶体管，通过使用不同能量的单独注入来实现最佳定位。 用于形成栅极导体的多晶硅层在图案化之前被掺杂，使得源极和漏极区域受到保护。 当植入诸如硼的快速扩散器时执行低能量注入，并且当植入像砷这样的慢扩散器时执行高能量注入。 这使得在施加热循环之后，杂质在整个栅极导体横截面中的最佳定位。 最初放置快速扩散器远离多晶硅的底表面，并在加热时在多晶硅的底表面附近扩散。 缓慢扩散器最初放置得更靠近多晶硅的底表面，因为它们不会容易地扩散。 使用与多晶硅植入物分开的非常低能量的注入来注入源极区和漏极区，以在半导体衬底内产生期望的浅源极和漏极区。

公开(公告)号：US5846876A

公开(公告)日：1998-12-08

申请号：US655244

申请日：1996-06-05

申请人： Basab Bandyopadhyay ,  H. Jim Fulford, Jr. ,  Robert Dawson ,  Fred N. Hause ,  Mark W. Michael ,  William S. Brennan

发明人： Basab Bandyopadhyay ,  H. Jim Fulford, Jr. ,  Robert Dawson ,  Fred N. Hause ,  Mark W. Michael ,  William S. Brennan

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L21/4763

CPC分类号： H01L21/76807 ,  H01L21/768 ,  H01L23/5222 ,  H01L2924/0002

摘要： An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. In densely spaced interconnect areas, interposed conductors are drawn to dissimilar elevational levels to lessen the capacitive coupling between the interconnects. By staggering every other interconnect line in the densely patterned areas, the interconnects are capable of carrying a larger amount of current with minimal capacitive coupling therebetween.

公开(公告)号：US5814555A

公开(公告)日：1998-09-29

申请号：US658456

申请日：1996-06-05

申请人： Basab Bandyopadhyay ,  H. Jim Fulford, Jr. ,  Robert Dawson ,  Fred N. Hause ,  Mark W. Michael ,  William S. Brennan

发明人： Basab Bandyopadhyay ,  H. Jim Fulford, Jr. ,  Robert Dawson ,  Fred N. Hause ,  Mark W. Michael ,  William S. Brennan

IPC分类号： H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/02164 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/31612 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002

摘要： A reduced permittivity interlevel dielectric in a semiconductor device arranged between two levels of interconnect. The dielectric comprises a first dielectric layer preferably from a silane source deposited on a first level interconnect to form air gaps at midpoints between adjacent first interconnect structures, a second dielectric containing air gap trenches at spaced intervals across the second dielectric, and a third dielectric formed upon said second dielectric. A second interconnect level is formed on the third dielectric.

摘要翻译： 布置在两层互连之间的半导体器件中的介电常数介电层的介电常数降低。 电介质包括第一电介质层，优选地来自沉积在第一级互连上的硅烷源，以在相邻的第一互连结构之间的中点处形成气隙;第二电介质，其以间隔开的间隔跨越第二电介质包含气隙沟槽，以及形成的第三电介质 在所述第二电介质上。 在第三电介质上形成第二互连电平。

公开(公告)号：US5679605A

公开(公告)日：1997-10-21

申请号：US658458

申请日：1996-06-05

申请人： William S. Brennan ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Fred N. Hause ,  Basab Bandyopadhyay ,  Mark W. Michael

发明人： William S. Brennan ,  Robert Dawson ,  H. Jim Fulford, Jr. ,  Fred N. Hause ,  Basab Bandyopadhyay ,  Mark W. Michael

IPC分类号： H01L21/768 ,  H01L21/441

CPC分类号： H01L21/76877

摘要： A multilevel interconnect structure is provided. The multilevel interconnect structure includes two, three or more levels of conductors formed according to at least two exemplary embodiments. According to one embodiment, the contact structure which links conductors on one level to an underlying level is formed by a single via etch step followed by a fill step separate from a fill step used in filling the via. In this embodiment, the via is filled with a conductive material which forms a plug separate from the material used in forming the interconnect. In another exemplary embodiment, the step used in filling the via can be the same as that used in forming the interconnect. In either instance, a via is formed through a first dielectric to underlying conductors. A second dielectric is patterned upon the first dielectric and serves to laterally bound the fill material used in producing the overlying interconnect. Regardless of the process sequence chosen, the interlevel dielectric structure is left substantially planar in readiness for subsequent interconnect levels dielectically deposited thereon.

摘要翻译： 提供了多层互连结构。 多层互连结构包括根据至少两个示例性实施例形成的两层，三层或更多级的导体。 根据一个实施例，通过单个通孔蚀刻步骤形成将一个层上的导体连接到下层的接触结构，随后是与用于填充通孔的填充步骤分离的填充步骤。 在该实施例中，通孔填充导电材料，该导电材料形成与用于形成互连件的材料分开的插头。 在另一个示例性实施例中，用于填充通孔的步骤可以与在形成互连中使用的步骤相同。 在任一情况下，通孔通过第一电介质形成到下面的导体。 在第一电介质上构图第二电介质，并且用于横向地限制用于制造上覆互连的填充材料。 不管选择的工艺顺序如何，层间电介质结构留在基本上平坦的准备中，用于介于其上的后续互连层。

公开(公告)号：US4701780A

公开(公告)日：1987-10-20

申请号：US903200

申请日：1986-12-05

申请人： Kevin T. Hankins ,  Mark W. Michael ,  Jay D. Moser ,  Brian K. Rosier

发明人： Kevin T. Hankins ,  Mark W. Michael ,  Jay D. Moser ,  Brian K. Rosier

IPC分类号： H01L21/033 ,  H01L21/768 ,  H01L23/525 ,  H01L27/02 ,  H01L27/12 ,  H01L29/04 ,  H01L29/34

CPC分类号： H01L23/5252 ,  H01L21/033 ,  H01L21/76888 ,  H01L2924/0002

摘要： A method of forming an aligned vertical oxide fuse and emitter using a single mask. The mask includes an opening through which impurities are introduced into the base region through a first layer of insulation and which is subsequently used to form the emitter aperture through the first insulative layer. The thin fuse oxide is formed by non-selective oxidation after removal of the mask. Alternatively, the impurities may also be introduced through the emitter aperture or from doped thin fuse oxide after removal of the mask. The resulting integrated circuit includes at least three regions of oxidation of three thicknesses, in descending order, field oxide, device opening or gate oxide and fuse oxide.

摘要翻译： 使用单个掩模形成对准的垂直氧化物熔丝和发射体的方法。 掩模包括开口，通过该开口，杂质通过第一绝缘层被引入基底区域中，随后用于通过第一绝缘层形成发射器孔。 除去掩模之后，通过非选择性氧化形成薄熔丝氧化物。 或者，杂质也可以在除去掩模之后通过发射器孔或掺杂的薄熔丝氧化物引入。 所得到的集成电路包括三个厚度的氧化的至少三个区域，按降序，场氧化物，器件开路或栅极氧化物和熔丝氧化物。

公开(公告)号：US4635345A

公开(公告)日：1987-01-13

申请号：US711816

申请日：1985-03-14

申请人： Kevin T. Hankins ,  Mark W. Michael ,  Brian K. Rosier

发明人： Kevin T. Hankins ,  Mark W. Michael ,  Brian K. Rosier

IPC分类号： H01L21/033 ,  H01L23/525 ,  H01L21/20 ,  H01L21/479

CPC分类号： H01L23/5252 ,  H01L21/033 ,  H01L2924/0002 ,  Y10S438/981

摘要： A method of forming an aligned vertical oxide fuse and emitter using a single mask. The mask includes an opening through which impurities are introduced into the base region through a first layer of insulation and which is subsequently used to form the emitter aperture through the first insulative layer. The thin fuse oxide is formed by non-selective oxidation after removal of the mask. Alternatively, the impurities may also be introduced through the emitter aperture or from doped thin fuse oxide after removal of the mask. The resulting integrated circuit includes at least three regions of oxidation of three thicknesses, in descending order, field oxide, device opening or gate oxide and fuse oxide.

摘要翻译： 使用单个掩模形成对准的垂直氧化物熔丝和发射体的方法。 掩模包括开口，通过该开口，杂质通过第一绝缘层被引入基底区域中，随后用于通过第一绝缘层形成发射器孔。 除去掩模之后，通过非选择性氧化形成薄熔丝氧化物。 或者，杂质也可以在除去掩模之后通过发射器孔或掺杂的薄熔丝氧化物引入。 所得到的集成电路包括三个厚度的氧化的至少三个区域，按降序，场氧化物，器件开路或栅极氧化物和熔丝氧化物。